Week In Review: Design, Low Power

By Jesse Allen - 14 Oct, 2022 - Comments: 0

Cadence unveiled a new environment to automate and accelerate the complete design closure cycle from signoff optimization through routing, static timing analysis (STA), and extraction. The Certus Closure Solution allows concurrent, full-chip optimization through a massively parallel and distributed architecture and engine shared with Cadence’s Innovus Implementation System and the Tempus Timi... » read more

Energy Harvesting Starting To Gain Traction

By John Koon - 18 Apr, 2022 - Comments: 4

Tens of billions of IoT devices are powered by batteries today. Depending on the compute intensity and the battery chemistry, these devices can run steadily for short periods of time, or they can run occasionally for decades. But in some cases, they also can either harvest energy themselves, or tap into externally harvested energy, allowing them to work almost indefinitely. Energy harvesting... » read more

Where Is Energy Harvesting?

By Kevin Fogarty - 05 Apr, 2018 - Comments: 0

With power management a top priority in sensor networks, why is energy harvesting—a proven technology with diverse energy sources—conspicuously absent from sensor designs that are the foundation of the Internet of Things? [getkc id="165" kc_name="Energy harvesting"] always has been a promising answer to the limits of battery power. The idea that a device can run for much longer periods o... » read more

Life Without Batteries Or Wires

By Ed Sperling - 15 Apr, 2009 - Comments: 0

By Ed Sperling In portable devices, low-power design has always been about stretching out the amount of time between battery charges or replacement. But the focus of current research throws that approach to the wind. The new goal is to get rid of batteries altogether and generate power using a variety of different mechanisms ranging from differences in temperature, the motion of waves, static... » read more

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Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

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Week In Review: Design, Low Power

Energy Harvesting Starting To Gain Traction

Where Is Energy Harvesting?

Life Without Batteries Or Wires

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