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Week In Review: Manufacturing, Test


Packaging ASE, AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC have announced the formation of a consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. The founding companies also ratified the UCIe specification, an open industry standard developed to establish a standard interconnect at the package level. The UCIe 1.0 s... » read more

Manufacturing Bits: July 20


Interference EUV lithography ESOL has developed a standalone interference extreme ultraviolet (EUV) lithography tool for use in R&D applications. The system, called EMiLE (EUV Micro-interference Lithography Equipment), is primary used to speed up the development of EUV photoresists and related wafer processes. The system is different than ASML’s EUV lithography scanners, which are ... » read more

Finding Defects In EUV Masks


Extreme ultraviolet (EUV) lithography is finally in production at advanced nodes, but there are still several challenges with the technology, such as EUV mask defects. Defects are unwanted deviations in chips, which can impact yield and performance. They can crop up during the chip manufacturing process, including the production of a mask or photomask, sometimes called a reticle. Fortunately... » read more