Luminary Panel Sees Progress In EUV Pellicle Adoption As Critical For EUV

By Jan Willis - 21 Nov, 2024 - Comments: 0

A significant focus of the 2024 SPIE Photomask and EUV conference was on EUV lithography and high-numerical-aperture (high-NA) EUV lithography, offering the potential to drive resolution to new heights. These EUV solutions bring new challenges such as pellicles, mask inspection, and smaller and smaller minimum mask dimensions. Progress has been impressive, according to lithography luminary Dr. ... » read more

Tuning Design And Process For High-NA EUV Stitching

By Kevin Lucas - 24 Oct, 2024 - Comments: 0

By Kevin Lucas and James Ban Upcoming 14A and 10A process nodes will use high-NA EUV anamorphic scanners, which will require two stitched half-fields to achieve the equivalent wafer exposure area of previous-generation scanners, see figure 1. The lithography patterning at a stitching boundary between two mask exposures will be affected by additional process variation than are encountered in ... » read more

Luminary Panel Sees Multi-Beam Mask Writers And Curvilinear Masks Key To 193i And EUV

By Jan Willis - 24 Oct, 2024 - Comments: 0

Attendance was up and the mood was optimistic at this year’s SPIE Photomask and EUV conference held September 29 through October 3, 2024. The optimism was apparent as well for multi-beam mask writers and curvilinear masks during the eBeam Initiative’s 15th annual reception and meeting held on October 1. In the eBeam Initiative’s annual Luminaries survey, 93% of those surveyed said that pu... » read more

Research Bits: Aug. 20

By Jesse Allen - 20 Aug, 2024 - Comments: 0

EUV mirror interference lithography Researchers from the Paul Scherrer Institute developed an EUV lithography technique that can produce conductive tracks with a separation of just five nanometers by exposing the sample indirectly rather than directly. Called EUV mirror interference lithography (MIL), the technique uses two mutually coherent beams that are reflected onto the wafer by two id... » read more

Research Bits: Aug. 13

By Jesse Allen - 13 Aug, 2024 - Comments: 0

3D X-ray of chip interiors Researchers from the Paul Scherrer Institute, EPFL Lausanne, ETH Zurich, and the University of Southern California used X-rays to take non-destructive, three-dimensional images of the inside of a microchip at 4 nanometer resolution. To create the images, the researchers relied on a technique called ptychography, in which a computer combines many individual images ... » read more

Legacy Process Nodes Going Strong

By Bryon Moyer - 23 Jul, 2024 - Comments: 0

While all eyes tend to focus on the leading-edge silicon nodes, many mature nodes continue to enjoy robust manufacturing demand. Successive nodes stopped reducing die cost at around the 20nm node. “In the finFET era of processes, esoteric process requirements necessary to move technology forward with each generation have added significant cost and complexity,” explained Andrew Appleby, p... » read more

European Mask And Lithography Conference 2024 Worth Attending

By Asmus Hetzel - 23 Jul, 2024 - Comments: 0

The European Mask and Lithography Conference (EMLC) 2024 recently was held in Grenoble, France, and had about 190 participants from a wide range of companies and institutions. Being relatively new to the field of lithography (my background is EDA, machine learning, optimization) and not being a fan of gigantic conferences, I thought it would be a good idea to visit this conference. My main p... » read more

Single Vs. Multi-Patterning Advancements For EUV

By Gregory Haley - 20 Jun, 2024 - Comments: 0

As semiconductor devices become more complex, so do the methods for patterning them. Ever-smaller features at each new node require continuous advancements in photolithography techniques and technologies. While the basic lithography process hasn’t changed since the founding of the industry — exposing light through a reticle onto a prepared silicon wafer — the techniques and technology ... » read more

A Wrap-Up Of Photomask Japan 2024

By Ingo Bork - 23 May, 2024 - Comments: 0

This year, I had the opportunity to attend the 30th Symposium on Photomask and NGL Mask Technology, also called Photomask Japan 2024 (PMJ), in Yokohama, Japan, from April 16 to 18. This well-regarded symposium brings together engineers from all over the world to share ideas on photomasks, NGL masks and related technologies. It was great being back to an in-person conference after four years ... » read more

The High NA EUV Imperative: How Computational Lithography Solutions Enable Us To Think Smaller

By Gandharv Bhatara - 21 Mar, 2024 - Comments: 0

The future of computing depends on miniaturization, and extreme ultraviolet lithography (EUV) is one key enabler. Until recently, we have relied on low numerical aperture (NA) EUV systems with an aperture of 0.33 to help us reduce the size of integrated circuits (ICs). As with deep ultraviolet (DUV) technology, this has begun to reach its limits. High NA EUV lithography with a 0.55 aperture rep... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

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by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?