Hybrid Bonding Makes Strides Toward Manufacturability

By Laura Peters - 28 Oct, 2024 - Comments: 0

Hybrid bonding is gaining traction in advanced packaging because it offers the shortest vertical connection between dies of similar or different functionalities, as well as better thermal, electrical and reliability results. Advantages include interconnect scaling to submicron pitches, high bandwidth, enhanced power efficiency, and better scaling relative to solder ball connections. But whil... » read more

Optimizing Wafer Edge Processes For Chip Stacking

By Laura Peters - 23 Sep, 2024 - Comments: 0

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower power consumption. The race is on to implement wafer stacking and die-to-wafer hybrid bonding, now considered essential for stacking logic and memory, 3D NAND, and possibly multi-layer DRAM stac... » read more

Powering CFETs From The Backside

By Katherine Derbyshire - 21 Mar, 2024 - Comments: 0

The first CMOS circuits to incorporate backside power connections are likely to be based on stacked nanosheet transistors, but further down the road, planners envision complementary transistors (CFETs) that vertically integrate stacked NFET and PFET devices. With at least twice the thickness of a nanosheet transistor, connecting CFETs to each other and to the rest of the circuit is likely to... » read more

Rebalancing Test And Yield In IC Manufacturing

By Gregory Haley - 07 Nov, 2023 - Comments: 0

Balancing yield and test is essential to semiconductor manufacturing, but it's becoming harder to determine how much weight to give one versus the other as chips become more specialized for different applications. Yield focuses on maximizing the number of functional chips from a production batch, while test aims to ensure that each chip meets rigorous quality and performance standards. And w... » read more

Building Better Bridges In Advanced Packaging

By Laura Peters - 21 Sep, 2023 - Comments: 1

The increasing challenges and rising cost of logic scaling, along with demands for an increasing number of features, are pushing more companies into advanced packaging. And while that opens up a slew of new options, it also is causing widespread confusion over what works best for different processes and technologies. At its core, advanced packaging depends on reliable interconnects, well-def... » read more

Chiplets: Deep Dive Into Designing, Manufacturing, And Testing

By The SE Staff - 07 Aug, 2023 - Comments: 0

Chiplets are a disruptive technology. They change the way chips are designed, manufactured, tested, packaged, as well as the underlying business relationships and fundamentals. But they also open the door to vast new opportunities for existing chipmakers and startups to create highly customized components and systems for specific use cases and market segments. This LEGO-like approach sounds ... » read more

DAC/Semicon West Addresses Top Issues, Trends For Chips

By The SE Staff - 12 Jul, 2023 - Comments: 0

The Design Automation Conference (DAC) 2023 and Semicon West returned in full force this week, drawing in more attendees and sponsor companies than since before the pandemic. At times, booth traffic was four to five deep, blocking aisles, and standing room only was common at presentations. Hot topics included generative AI and the underlying semiconductor technology, data security, reliabili... » read more

True 3D-IC Problems

By Brian Bailey - 27 Apr, 2023 - Comments: 0

Placing logic on logic may sound like a small step, but several problems must be overcome to make it a reality. True 3D involves wafers stacked on top of each other in a highly integrated manner. This is very different from 2.5D integration, where logic is placed side-by-side, connected by an interposer. And there are some intermediate solutions today where significant memory is stacked on l... » read more

Week In Review: Semiconductor Manufacturing, Test

By Gregory Haley - 21 Apr, 2023 - Comments: 0

GlobalFoundries filed suit in U.S. District Court in New York against IBM, accusing it of unlawfully disclosing IP and trade secrets to IBM partners, including Intel and Rapidus, potentially receiving hundreds of millions of dollars in licensing income and other benefits. The European Union released a €43 billion ($47 billion) plan for jumpstarting its semiconductor manufacturing industry,... » read more

Nanoimprint Finally Finds Its Footing

By Gregory Haley - 20 Apr, 2023 - Comments: 2

Nanoimprint lithography, which for decades has trailed behind traditional optical lithography, is emerging as the technology of choice for the rapidly growing photonics and biotech chips markets. First introduced in the mid-1990s, nanoimprint lithography (NIL) has consistently been touted as a lower-cost alternative to traditional optical lithography. Even today, NIL potentially is capable o... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?