Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V


A new technical paper titled "CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V" was published by researchers at TU Munich and Fraunhofer Institute for Applied and Integrated Security (AISEC). Abstract "Fault-injection attacks are a risk for any computing system executing security-relevant tasks, such as a secure boot process. While ha... » read more

What Makes A Chip Tamper-Proof?


The cyber world is the next major battlefield, and attackers are busily looking for ways to disrupt critical infrastructure. There is widespread proof this is happening. “Twenty-six percent of the U.S. power grid was found to be hosting Trojans," said Haydn Povey, IAR Systems' general manager of embedded security solutions. "In a cyber-warfare situation, that's the first thing that would b... » read more

Blog Review: Dec. 18


Lam Research's David Haynes finds that taking advances made at 300mm and applying them via upgrades to 200mm equipment is a cost appropriate strategy to quickly improve yield and add capacity. Synopsys' Taylor Armerding looks at which of this year's many data breaches hit corporate wallets the hardest and how the cost of privacy noncompliance is expected to rise with California's CCPA and st... » read more

Blog Review: April 17


In a video, Mentor's Colin Walls digs into power management in embedded software with a particular look at the Power Pyramid model. Synopsys' Taylor Armerding checks out the state of application security at this year's RSA and finds that while organizations are paying attention to security through training and dedicated teams, roadblocks still remain. Cadence's Paul McLellan considers how... » read more