Blog Review: Dec. 18

Applying 300mm techniques to 200mm; cost of data breaches; C bit fields; PTH and microvia issues.


Lam Research’s David Haynes finds that taking advances made at 300mm and applying them via upgrades to 200mm equipment is a cost appropriate strategy to quickly improve yield and add capacity.

Synopsys’ Taylor Armerding looks at which of this year’s many data breaches hit corporate wallets the hardest and how the cost of privacy noncompliance is expected to rise with California’s CCPA and stronger enforcement of the EU’s GDPR.

Mentor’s Colin Walls points out how potentially obsolete bit fields in C can be mistakenly used for an alternative application that can lead to less maintainable code and why the practice should stop.

Cadence’s Paul McLellan looks back at why Unix is the most influential operating system ever and how it unexpectedly came to be used in everyday devices.

Arm’s Karl Fezer reports from the Data Science Africa conference and workshop with a look at end-to-end data science, implementing ML in ultra-low power edge systems, and local mentorship.

ANSYS’ Natalie Hernandez examines why plated through hole and microvia structures cause fatigue failure in PCBs and how finite element analysis can help predict future problems.

In a video, VLSI Research’s Dan Hutcheson chats with Jim Handy of Objective Analysis about what will happen to the memory markets for DRAM and NAND in 2020, China’s progress in memory, and emerging memories.

A Rambus writer explains the Plundervolt software-based fault injection attack that can corrupt the integrity of Intel Software Guard Extensions to recover keys from cryptographic algorithms and induce memory safety vulnerabilities into bug-free enclave code.

SEMI’s Christian G. Dieseldorff finds that global fab equipment spending is slowly crawling out of its slump in the second half of 2019 with a pickup in investments in memory, leading-edge logic and foundries.

Western Digital’s Huibert Verhoeven considers the challenges ahead for autonomous and semi-autonomous vehicles, on-road testing, and V2X communications.

And don’t miss the blogs featured in the latest Manufacturing, Packaging & Materials and Low Power-High Performance newsletters:

Editor In Chief Ed Sperling points to why choreographing better yield is so difficult.

Applied Materials’ Buvna Ayyagari-Sangamalli warns that siloed structures that produced the computing eras of the past will not be sufficient to fuel AI.

Semico Research’s Rich Wawrzyniak shines a light how interconnect IP vendors will have more opportunities to help manage the complexity as designs include more IP blocks and subsystems.

SEMI’s Nishita Rao talks to Sandia’s Michael Holmes about the national lab’s move to 8-inch wafers and the development of a new infrared detector design.

Editor In Chief Ed Sperling looks at what comes after faster hardware and software.

Arm’s Carolyn Herzog calls for an industry-wide effort to take responsibility for a new set of ethical design system principles.

Mentor’s Mike Fingeroff explains how design teams are looking to new design and verification flows to meet the competitive time-to-market windows of edge AI.

Cadence’s Paul McLellan digs into new 3D packaging technologies that make it possible to combine die from different processes and suppliers.

Synopsys’ Ruud Derwig and Tortuga Logic’s Nicole Fern lay out three security rules to use when verifying secure processor IP.

ANSYS’ Sameer Kher details a collaboration to make developing digital twin platforms easier, even for proprietary systems.

Adesto’s Denise Rael describes why unboxing videos aren’t just for toys and smartphones.

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