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A Promising Future For Interconnect IP

As designs include more IP blocks and subsystems, interconnect IP vendors will have more opportunities to help manage the complexity.

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Complexity of SoC designs continues to increase primarily due to increased demand for functionality and performance in all electronic devices. Studies that Semico Research has conducted on the SoC design landscape shows the number of discrete SIP blocks has continued to rise in response to increased market requirements from new applications and richer feature sets.

Table 1: Comparison of 1st Time SoC Designs and Average SIP Block Growth Rates

Table 1 compares the 2018 – 2023 CAGR growth rates of 1st time SoC design efforts and the average number of SIP blocks used. It is not surprising that the largest rate of increase in average SIP blocks is found in the Advanced Performance Multicore SoC, while it has a moderate number of 1st time design efforts. Conversely, Basic SoCs have the highest growth rate for 1st time designs and the second highest growth rate in the average number of SIP blocks resident on chip. Basic SoCs are being used in IoT markets to provide basic functions and more recently, as a vehicle to provide AI (artificial intelligence) inference operations.

The emergence of AI (artificial intelligence) capabilities in even very low cost SoCs is driving increased interest in including more IP blocks in each design. Semico would go so far as to say that the advent of AI functionality has ignited a frenzy of architectural exploration and discovery in the semiconductor market providing a welcome opportunity to the industry to investigate new, non-traditional SoC processing architectures. This has created a landscape where changes in direction happen quickly based on new developments in the AI field.


Figure 1: Differing Levels of AI Functionality. Source: Semico Research Corp.

Figure 1 shows the different levels of AI as they are currently understood which are being deployed today or in the future. It is likely that an SoC will be required to have more than one type of AI functionality resident at any one time and be able to handle these different data streams and market requirements. Given the rate of improvements and advances in the AI field, it is possible we will see something close to a Level 4 AI within the forecast horizon.

New devices that offer more features, foster the use of more discrete SIP blocks and SIP subsystems in silicon solutions. The increased features and functions associated with AI as well as many new SoC designs, has led to an explosion in the number of SIP blocks and 3rd party SIP options. While there are different solutions to the increased complexity that these additional blocks add, one solution stands out as being the most successful, Interconnect SIP. Interconnect IP provides the mechanism that allows a cohesive design delivering the best opportunity for realizing the maximum possible performance.

Interconnect SIP lies at the heart of every SoC and allows designers to tie the many disparate SIP blocks together. This SIP type has evolved to the point where designers can rely on it to help with the floor planning of a design while still in the planning stage. This allows what-if scenarios to be proposed to arrive at the optimum configuration for SIP block arrangements and data flow. It can also provide security firewalls and power management functions.

SoC architectural design is not a simple undertaking given all the different discrete SIP blocks being used. The design must be created while delivering the best possible performance across all the different data streams present. In the case of interconnect SIP the situation is even more challenging because this type of SIP must interact with every other block in the design and must constantly be updated and refreshed as the other SIP blocks that attach to it evolve. As the internal central nervous system of the design, interconnect SIP touches everything in the design. As a result, the interconnect must be robust and modifiable without undue increases in design time. In addition to these requirements is the realization that a single design might be required to handle more than one level of AI functionality at a time depending on the application. A hypothetical example would be an AI-inference SoC that has a natural language interface (Level 1) which has a continuous learning function (Level 2) and that acts as a security expert (Level 3) in a manufacturing flow application. The inclusion of AI functionality adds to the need for sophisticated interconnect IP solutions.

This type of design will present an opportunity for interconnect vendors since few designers and companies have the expertise to create, maintain and update such complex solutions. While very large semiconductor companies do have the engineering resources to accomplish such interconnect solutions internally, most smaller companies do not, presenting an opportunity to the 3rd party interconnect SIP vendors.

It has been a long-held tenet of the 3rd party SIP market that the barriers to entry to becoming a SIP vendor are low as compared to becoming a semiconductor company. This is generally true since the large start-up costs associated with designing and producing a contemporary SoC are high and development costs for SIP are usually not. In the case of interconnect SIP vendors this is somewhat different. Most other SIP vendors are usually only developing one type of SIP and only need to concentrate on how their SIP product interacts with a few other blocks in the design; a CPU core with the embedded memory or with the SerDes channels as examples.

Because the evolutionary rates of these other blocks are all different, an interconnect SIP vendor must regularly interface with all the other SIP vendors to ensure these changes and improvements are captured. This is one reason why 3rd party interconnect IP is seeing more use and internal efforts at the SoC companies are becoming more difficult to accomplish. This established trend will continue to accelerate, especially as the SIP block count increases and SoC designs move to smaller process geometries.

As with most of the other categories of SIP today, there has been consolidation in the market with Sonics being acquired by Facebook and NetSpeed being acquired by Intel. This has left Arteris IP and Arm as the two main interconnect SIP vendors with newer companies such as Provino and OpenEdges entering the market.

Arteris and Arm have several interconnect IP products that enable complex types of SoC architectures and are enhancing these developments for products aimed at the emerging AI architectures.

  • The Arteris FlexNoC AI Package automatically generates mesh, ring and torus interconnect topologies. Unlike black box compiler approaches, SoC architects can edit generated topologies and also optimize each individual network router, if desired.
  • The FlexNoC Resilience Package complements FlexNoC fabric IP and implements hardware reliability & functional safety features required for automotive ISO 26262 or IEC 61508 compliance, and enhanced enterprise SSD endurance.
  • The Ncore Cache Coherent Interconnect IP offers multiple configurable snoop filters, multiple configurable proxy caches and a modular, distributed architecture to provide system architects the most advanced technology and more degrees of freedom to innovate.

ARM offers three interconnect IP products under the family name CoreLink. The ARM family provides a solution for the following.

  • CoreLink CMN-600 offers a highly configurable and scalable coherent mesh network solution designed for scaling to high performance infrastructure applications including networking and servers. It offers a scalable system coherency in multi-core heterogeneous processor systems.
  • CoreLink CCI-550, CCI-500, and CCI-400 offers a solution for Cache coherent interconnect, optimized for the high efficiency coherent applications including mobile big.LITTLE processing. This interconnect IP offers the smallest and lowest power multi-cluster interconnect from Arm.
  • CoreLink NIC-450, NIC-400 and NIC-301 offers a network interconnect solution, fully configurable for SoC connectivity across all applications. This product line offers hierarchical, low latency and low power connectivity and back plane for smaller, single processor designs. This product line is a companion interconnect for I/O coherency and other SoC connectivity with CoreLink Cache Coherent Interconnect and Coherent Mesh Network.

All these products are directed at reducing the level of design effort necessary to create and configure a complex SoC. The need for robust, maintainable interconnect SIP becomes even more important as designs migrate down the process geometry curve to 7nm and below. As these geometries and the transistors that inhabit them continue to shrink, unfortunately the wires connecting them do not. Therefore, a continuing need in complex designs is to efficiently route these wires to ensure the highest performance is achievable.

An efficient interconnect technology would allow designers to reduce the area taken up with the wiring network by allowing more efficient, automatic placement of the wires. This reduces the level of effort necessary for the wire routing and gives the designer more time to concentrate on other areas of the design. In addition to this benefit, other areas of improvement in the design effort are offered to the designer:

  1. Ease timing closure
  2. Enable higher operating frequencies
  3. Change IP easily
  4. Reduce wire routing congestion
  5. Power management capabilities
  6. Security functions and firewalls built in
  7. Offer a roadmap to the future for the designer to plan with

Based on these products and their attributes, Arteris is positioned to continue as a leader in the interconnect SIP market. In addition, continuing improvements in the breadth and scope of interconnect SIP argue for even more intelligence being infused into this type of product to the benefit of SoC designers. Arteris has a vision of what benefits and improvements interconnect SIP can bring to SoC designers and they are acting on this vision. Arteris continues to introduce innovative SIP to help power the new age of architectural exploration and discovery the advent of AI has unleashed. This new wave of innovation is occurring at just the right time to keep the market growing and Arteris continues to innovate right along with this trend. Something every leader does.



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