tag: finFETs

A Paradigm Shift With Vertical Nanowire FETs For 5nm And Beyond
By Taigon Song - 27 Sep, 2018 - Comments: 1

When I was in undergrad not so long ago, all my circuits and semiconductor textbooks/professors were talking about MOSFETs (metal-oxide semiconductor field-effect transistor) that were just “better” than BJTs (bi-polar junction transistor). There were still some old professors talking about how they did an excellent job using BJTs, but everyone knew it was MOSFET that was leading the game i... » read more

Advanced Defect Inspection Techniques For nFET And pFET Defectivity At 7nm Gate Poly Removal Process
By KLA - 20 Sep, 2018 - Comments: 0

By Ian Tolle, GlobalFoundries, and Michael Daino, KLA-Tencor During 7nm gate poly removal process, polysilicon is removed exposing both NFET and PFET fins in preparation for high-k gate oxide. If the polysilicon etch is too aggressive or the source and drain are not sufficiently protected, the etch can damage the active region and render the FET inoperative. Different materials are used in t... » read more

The Security Penalty
By Ed Sperling - 13 Sep, 2018 - Comments: 0

It's not clear if Meltdown, Spectre and Foreshadow caused actual security breaches, but they did prompt big processor vendors like Intel, Arm, AMD and IBM to fix these vulnerabilities before they were made public by Google's Project Zero. While all of this may make data center managers and consumers feel better in one respect, it has created a level of panic of a different sort. For decades,... » read more

Where FD-SOI Works Best (Part 2)
By Ed Sperling - 15 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss changes in the FD-SOI world and what's behind them, with James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science; Giorgio Cesana, director of technical marketing at STMicroelectronics; Olivier Vatel, senior vice president and CTO at Screen Semiconductor Solutions; and Carlos Mazure, CTO at Soi... » read more

Who’s Paying For Auto Chip Test?
By Ed Sperling - 06 Aug, 2018 - Comments: 0

Testing of automotive chips is becoming more difficult and time-consuming, and the problem is only going to get worse. There is more to this than simply developing new test equipment or devising a better design for test flow. There are multiple issues at play here, and some of them are at odds with the others. First, no one has experience using advanced-node chips in extreme environments.... » read more

On-Chip Monitoring Of FinFETs
By Ed Sperling - 25 Jul, 2018 - Comments: 0

Stephen Crosher, CEO of Moortec, sat down with Semiconductor Engineering to discuss on-chip monitoring and its impact on power, security and reliability, including predictive maintenance. What follows are excerpts of that conversation. SE: What new problems are you seeing in design? Crosher: There are challenges emerging for companies working on advanced nodes, including scaling and trans... » read more

The Financial Justification For System-Level Test
By Astronics - 23 Jul, 2018 - Comments: 0

Three unique trends are currently transforming high-volume manufacturing in the semiconductor industry: The increasing complexity of chip architectures (e.g., FinFET, heterogeneous integration); The explosion in the breadth and ubiquity of consumer electronics (e.g. IoT, mobile, and automotive), and Consumer expectations of a constant stream of newer, cheaper, more advanced nodes. ... » read more

Five DAC Keynotes
By Brian Bailey - 17 Jul, 2018 - Comments: 0

The ending of Moore's Law may be about to create a new golden age for design, especially one fueled by artificial intelligence and machine learning. But design will become task-, application- and domain-specific, and will require that we think about the lifecycle of the products in a different way. In the future, we also will have to design for augmentation of experience, not just automation... » read more

7nm Design Challenges
By Ed Sperling - 09 Jul, 2018 - Comments: 0

Ty Garibay, CTO at ArterisIP, talks about the challenges of moving to 7nm, who’s likely to head there, how long it will take to develop chips at that node, and why it will be so expensive. This also raises questions about whether chips will begin to disaggregate at 7nm and 5nm. https://youtu.be/ZqCAbH678GE » read more

FinFET ASICs: It Takes A Platform
By Mike Gianfagna - 28 Jun, 2018 - Comments: 0

Sophisticated, specialized ASIC technology is making an impact on the everyday world around us. Whether it’s a gadget you can have a conversation with, a car that will take over driving from time to time, or internet speeds that seem impossibly fast, there is likely sophisticated custom silicon present as a critical enabling technology. Plenty has been written about advanced ASICs for network... » read more

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