Where FD-SOI Works Best

Experts at the Table, part 2: Why FD-SOI is being used alongside finFETs and other technologies, and what are the key drivers for chipmakers.

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Semiconductor Engineering sat down to discuss changes in the FD-SOI world and what’s behind them, with James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science; Giorgio Cesana, director of technical marketing at STMicroelectronics; Olivier Vatel, senior vice president and CTO at Screen Semiconductor Solutions; and Carlos Mazure, CTO at Soitec and chairman of the SOI Consortium. What follows are excerpts of that conversation. To read part one, click here.


L-R: James Lamb, Giorgio Cesana, Olivier Vatel, Carlos Mazure.

SE: Variation in biasing is a new area of concern. How does that affect designs?

Cesana: There are many sources of variability. If you put the power supply on the bias, there are plenty of parameters like threshold voltage and gain, but the stability of the supply will impact the variability. You need the body bias to manage that. But if you do analog with the bias, you need a bias generator that is more robust than if you just do digital design, where you add additional margin and so on. Analog designers know how to manage all of this very well.

Mazure: This is not specific to FD-SOI. You use a lot of PVT blocks in analog. Mixed signal is subject to this type of variability, with more or less degree, depending on the technology node and other factors.

Cesana: At the same time, you have a lot of opportunity. If you think about all the PVT compensation that you traditionally do in analog design, where you don’t have body bias, you have to compensate with the voltage. So you put a regulator on the main supply, which means the available voltage for the analog block is lower because you have to remove what you lose in the compensating circuit. With body bias, you remove all of that, so your analog will see the full Vdd swing, which is good. You have to better control the body bias, but this body bias is compensating for the variability aspect of the Vdd. You mitigate, you don’t really compensate. You are are touching the parameters that you want to control, so you can get much better results in the end—smaller circuits and lower power.

SE: At 7/5nm we are now dealing with issues like noise that analog designers wrestled with in the past. Is this an opportunity for FD-SOI.

Cesana: You can pick what is more convenient for what you have to do. With finFETs, at 7nm or future nodes, the solution is to put a big ADC in there and do everything in digital. FD provides the leverage to still design analog and RF. If you want to make a 5G module with beam forming in millimeter wave, on the antenna side it makes sense to do it in digital. But on the phone, doing it in analog is much lower power. With finFETs you don’t have much choice. With FD-SOI, in the end you can reduce the power.

Mazure: But this is not a choice of 7nm finFETs or 28/22nm FD-SOI. We’re working in a different space.

SE: Yes, but we are reaching a level of granularity with heterogeneous computing that we didn’t have in the past.

Mazure: For the foundries offering 28 or 22nm, at the end of the day the price of wafers will have to be competitive and attractive—with the additional benefits of using FD-SOI. And that is the case today. This is why tablets are getting interested in this technology. These IoT applications that are so cost-sensitive are very interested in FD-SOI, too. But the cost issue is not really the first consideration for a lot of applications. We have become a very power-centric industry. Power is the name of the game.

Vatel: Our tools have a lot of sensors, and our latest tool has 24 chambers. We are lowering the cost as far as we can for sensing with FD-SOI. On the equipment side, this reduces the cost for us.

Lamb: We are in the sensor business. We’re developing technologies for IoT or industrial sensors, and we’re very interested in FD-SOI for processing, alarms, and sending data about various conditions back to a database. There are two very different sides to this market. At the edge we are trying to collect a lot of data and condition it before sending it on to the servers in the cloud, which is driving the other side of the business. We think both sides have a lot of growth potential.

SE: Is the key metric cost or power, or both?

Lamb: Power is our primary concern. You can have a fairly high cost in certain markets, but to get to large volume markets you need to get the cost down. Right now, though, the real issue is power.

Mazure: In a presentation, Audi said that power constraints are very important in a car, too.

SE: We are basically running data centers on wheels with autonomous vehicles, right?

Mazure: Absolutely, and there are more sensors with intelligence, and they all have to be low power. We need FD-SOI for that because we need an ultra-low-power capability. As we add more sensors, we add more and more local-node computing. We cannot continue to keep increasing the power budget of the car. On the contrary, we have to reduce it. Even big system integrators are asking for this.

Cesana: And just because we are 28nm and 22nm does not mean there are not constraints on materials, equipment and metrology. We are dealing with very complex designs with many challenges from both digital and analog. RF is getting more and more important. Designers can always adapt and put margin into designs, but every time we add margin it’s extra cost and it takes more power. But these also have to be uniform lines and spaces. The equipment is key.

SE: As we move into heterogeneous computin, we’re starting to partition functionality in different ways. So you may have an RF-SOI or FD-SOI with a 10nm logic chip. What gets used for which applications?

Cesana: It’s always about the right technical choice that is cost-optimized. In the past, we developed some advanced packaging that the customer said was too expensive. Maybe the technology wasn’t measuring up and it was increasing the cost. But we are in production with 2.5D integration with silicon photonics. The photonics is on FD-SOI in one chip, and BiCMOS for the electronics interface on the other, and they are glued together. It’s getting much more complicated. A package has two or three or four different devices from different technologies.

Mazure: You can pick one of these and one of these. You have RF for transmission and reception. There are different specs. And today all of this is done with RF-SOI technology. Companies are adding more complexity. The application processor is very complex and peformance-driven, so it’s finFETs.

SE: What happens with aging and reliability? As these chips are used in more safety-critical applications, does FD-SOI age the same way as standard bulk CMOS?

Lamb: It looks as if FD-SOI is more reliable over time and at different temperature ranges. But some of that may just be due to scaling. If you back off a few nanometers in finFETs, they may be more reliable. It’s not clear yet. But SOI is less temperature-sensitive, and it has a longer lifetime.

Mazure: Airbus also found it was more robust when it comes to radiation.

Vatel: GlobalFoundries found that FD-SOI was more robust at 22nm for automotive applications, too. FinFETs so far have not been automotive-certified, although I would be very surprised if that doesn’t happen. But FD-SOI is already there.



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