The Race To Glass Substrates

By Gregory Haley - 29 May, 2024 - Comments: 4

The chip industry is racing to develop glass for advanced packaging, setting the stage for one of the biggest shifts in chip materials in decades — and one that will introduce a broad new set of challenges that will take years to fully resolve. Glass has been discussed as a replacement material for silicon and organic substrates for more than a decade, primarily in multi-die packages. But ... » read more

Fan-Out Panel-Level Packaging Hurdles

By Anne Meixner - 24 Jan, 2024 - Comments: 0

Fan-out panel-level packaging (FOPLP) promises to significantly lower assembly costs over fan-out wafer-level packaging, providing the relevant processes for die placement, molding and redistribution layers (RDLs) formation can be scaled up with equivalent yield. There is still much work to be done before that happens. Until now, FOPLP has been adopted for devices that are manufactured in ve... » read more

Fan-Out Packaging Gets Competitive

By Karen Heyman and Laura Peters - 18 Aug, 2022 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

Advanced Outlier Die Control Technology In Fan-Out Panel Level Packaging Using Feedforward Lithography

By Onto Innovation - 12 Oct, 2021 - Comments: 0

The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels. Fan-out panel level packaging (FOPLP) is one of the technologies that... » read more

What Does It Take To Build A Successful Multi-Chip Module Factory?

By Mike McIntyre - 06 Jul, 2021 - Comments: 0

When it comes to multi-chip module (MCM) manufacturing, fan-out wafer-level and fan-out panel-level packaging have received a lot of coverage recently. Every week, it seems like there is an announcement about “Company XYZ” moving their products into the fan-out wafer-level packaging (FOWLP) or fan-out panel-level packaging (FOPLP) space. But these moves come with challenges that didn’t ex... » read more

Adaptive Shot Technology To Address Severe Lithography Challenges For Advanced FOPLP

By Onto Innovation - 07 Dec, 2020 - Comments: 0

Fan-out wafer level packaging (FOWLP) is a popular new packaging technology that allows the user to increase I/O in a smaller IC size than fan-in wafer level packaging. Market drivers such as 5G, IoT, mobile and AI will all use this technology. According to Yole Développement’s analysis, the fan-out packaging market size will increase to $3 billion in 2022 from $2.44 hundred million in 2014,... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer