Renesas Solves High-Level Verification Challenges Using Formal Equivalence Checking


A team at Renesas Electronics Corporation found that they were significantly reducing the time advantages of their High-Level Synthesis flow due to bugs in their SystemC code and equivalence problems due to design changes. It was taking too much time to find and debug these issues and some bugs were slipping into the generated RTL. To solve these challenges, they added SLEC®, which is the form... » read more

Debugging Debug


There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more