tag: formal verification

Which Verification Engine? (Part 2)
By Ed Sperling - 06 Dec, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Dealing With Deadlocks
By Ann Mutschler - 26 Oct, 2017 - Comments: 1

Deadlocks are becoming increasingly problematic as designs becoming more complex and heterogeneous. Rather than just integrating IP, the challenge is understanding all of the possible interactions and dependencies. That affects the choice of IP, how it is implemented in a design, and how it is verified. And it adds a whole bunch of unknowns into an already complex formula for return on inves... » read more

Verifying AI, Machine Learning
By Ed Sperling - 28 Sep, 2017 - Comments: 0

[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down to talk about artificial intelligence, machine learning, and neuromorphic chips. What follows are excerpts of that conversation. SE: What's changing in [getkc id="305" kc_name="machine learning"]? Brinkmann: There’s a real push toward computing at the edge. ... » read more

Verification’s Breaking Points
By Ann Mutschler - 28 Sep, 2017 - Comments: 2

Verification efficiency and speed can vary significantly from one design to the next, and that variability is rising alongside growing design complexity. The result is a new level of unpredictability about how much it will cost to complete the verification process, whether it will meet narrow market windows, and whether quality will be traded off to get a chip out on time in the hopes that it c... » read more

Machine Learning In The Fab
By Ed Sperling - 17 Aug, 2017 - Comments: 0

Machine learning is exploding, especially where there are massive amounts of data to contend with and lots of potential interactions. This leads to two obvious insertion points in the semiconductor field. One is on the design side, where just getting an advanced design to function is an enormous challenge. That challenge increases as the need for reliability in some market increases. It's d... » read more

How Much Verification Is Necessary?
By Ann Mutschler - 27 Jul, 2017 - Comments: 0

Since the advent of IC design flows, starting with RTL descriptions in languages like Verilog or VHDL, project teams have struggled with how much verification can and should be performed by the original RTL developers. Constrained-random methods based on high-level languages such as [gettech id="31021" t_name="e"] or [gettech id="31023" comment="SystemVerilog"] further cemented the role of t... » read more

Using Formal To Verify Safety-Critical Hardware For ISO 26262
By Sergio Marchese - 26 Jul, 2017 - Comments: 0

Automotive technology has come a long way since the days of the Ford Model T. Today's smart vehicles not only assist their drivers with tasks such as parking, lane management, and braking, but also function as a home away from home, with WiFi hotspots and sophisticated entertainment systems. These sophisticated features are made possible by increasingly complex electronic systems—systems that... » read more

Verification Unification
By Brian Bailey - 03 Jul, 2017 - Comments: 0

Semiconductor Engineering brought together industry luminaries to initiate the discussion about the role that formal technologies will play with the recently released early adopter's draft of Portable Stimulus and how it may help to bring the two execution technologies closer together. Participating in this roundtable are Joe Hupcey, verification product technologist for [getentity id="22017" e... » read more

Hybrid Emulation
By Brian Bailey - 29 Jun, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Verification And The IoT
By Ed Sperling - 28 Jun, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss what impact the IoT will have on the design cycle, with Christopher Lawless, director of external customer acceleration in [getentity id="22846" e_name="Intel"]'s Software Services Group; David Lacey, design and verification technologist at Hewlett Packard Enterprise; Jim Hogan, managing partner at Vista Ventures; Frank Schirrmeister, senior group d... » read more

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