Can Verification Meet In The Middle?


Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

Achieving 100% Functional Coverage By Operational Assertion-Based Verification


This white paper presents Operational Assertion-Based Verification (ABV), an advanced formal verification methodology resulting in a predictable, small number of high-level assertions capturing the functionality of a design. Operational ABV enables an automatic formal coverage analysis, which identifies holes in verification plans, unverified design functionality as well as errors and omissio... » read more

Formal Confusion


Semiconductor Engineering sat down to discuss the right and wrong ways to apply formal verification technology with Normando Montecillo, associate technical director at [getentity id="22649" comment="Broadcom"]; Ashish Darbari, principal engineer at [getentity id="22709" e_name="Imagination Technologies"]; Roger Sabbagh, principal engineer at Huawei; and Stuart Hoad, lead engineer at PMC Sierra... » read more

The Top Five Trends in Verification to Watch for at DAC 2016


The Design Automation Conference in Austin is upon us, so it's time for my annual preview of what to look for. In my mind, five trends stand out and are clearly visible in the DAC program as well as in what we are presenting at our booth: Stronger ties between verification engines Software-driven verification with portable stimulus Metric-driven verification Application specificity ... » read more

Formal Confusion


Formal verification has come a long way in the past five years. Tool developers changed direction and started to create self-contained apps which have led to a rapid proliferation of the technology. But formal is a diverse set of tools that can solve a variety of problems in the verification space and this has created a different kind of confusion within the industry. To find out how the indust... » read more

Grappling With IoT Security


By Ed Sperling & Ernest Worthman As the IoT begins to take shape, the security implications of connecting devices and systems to the Internet and what needs to be done to secure them are coming into focus, as well. There is growing consensus across the semiconductor industry that many potential security holes remain, with new ones surfacing all the time. But there also is widespread r... » read more

Are Simulation’s Days Numbered?


Semiconductor Engineering sat down to discuss the limitations of simulation in more complex designs with [getperson id="11049" comment="Michael McNamara"], CEO of [getentity id="22716" comment="Adapt-IP”]; Pete Hardee, product management director at [getentity id="22032" e_name="Cadence"]; David Kelf, vice president of marketing for for [getentity id="22395" e_name="OneSpin Solutions"]; Lauro... » read more

Are Simulation’s Days Numbered?


Semiconductor Engineering sat down to discuss the limitations of simulation in more complex designs with [getperson id="11049" comment="Michael McNamara"], CEO of [getentity id="22716" comment="Adapt-IP”]; Pete Hardee, product management director at [getentity id="22032" e_name="Cadence"]; David Kelf, vice president of marketing for [getentity id="22395" e_name="OneSpin Solutions"]; Lauro Riz... » read more

A Formal Transformation


A very important change is underway in functional verification. In the past, this was an esoteric technology and one that was difficult to deploy. It was relegated to tough problems late in the verification cycle, and it was difficult to justify the ROI unless the technology actually did find some problems. But all of that has changed. Formal verification companies started to use the technology... » read more

Everything You Wanted to Know About Formal, But Were Too Afraid to Ask


Formal Verification is one of those EDA technologies that's been used in mainstream development in one or two applications for many years. The true power of the approach only now has started to capture the attention of engineers. Although there are a few reasons for this, perhaps the most significant is formal’s ill-gotten reputation as a mysterious beast too difficult to tame. After worki... » read more

← Older posts Newer posts →