The New Face Of Formal


Semiconductor Engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager of R&D in the verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphic... » read more

Property Synthesis Throughout The Design Flow For Application In Formal Verification, Simulation, And Emulation


This white paper describes the JasperGold Property Synthesis Apps, members of a family of interoperable, application-specific formal verification solutions that addresses verification challenges throughout the design flow. The Apps synthesize both behavioral and structural properties — also known as assertions — for use in formal verification, simulation and emulation. They significantly in... » read more

Power Breaks Everything


The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won't go away. In the past, most issues involving power—notably current leakage, physical effects such... » read more

Formal Verification For Post-Silicon Debug


Bug escape costs grow considerably with each and every subsequent step in the design flow, to the point of being exorbitantly high once at the silicon level. As a result, these high costs of bug escape are driving customers to embrace formal verification for post-silicon debug and to begin using formal far earlier in the flow for their next design projects. The Cadence JasperGold Verification S... » read more

Full Coverage Or Full Monty


Without adequate coverage metrics and tools, verification engineers would never be able to answer the proverbial question: Are we done yet? But a lot has changed in the design flow since the existing set of metrics was defined. Does it still ensure that the right things get verified, that time is not wasted on things deemed unimportant or a duplication of effort, and can it handle today’s hie... » read more

Taming Lint With Formal


Designers have been using Linting tools for many years to ensure designs adhere to recommended coding guidelines. Linting tools verify that RTL is written in an unambiguous way to ensure that downstream tools (simulation, synthesis, etc.) do not interpret the code incorrectly, resulting in design, verification, timing or implementation issues. Linting tools take advantage of fast and shallow... » read more

Does Fast Simulation Help Debug Productivity?


It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by [getentity id="22032" e_name="Cadence"] at the recent Design and Verification Conference (DVCon) in Santa Clara, CA. Brian Bailey, technology editor for Semiconductor Engineer was the moderator for the panel and broke the news to the crowd. Cadence had developed a logic [getkc id... » read more

Tech Talk: Better Coverage


Atrenta's Yuan Lu talks about code coverage, functional coverage and the use of assertions in debugging designs. [youtube vid=Hpm-l1z8HTo] » read more

Clock Domain Crossing (CDC): Are We There Yet?


Over the last decade, SoC designs have become significantly reliant on IP reuse to manage the design complexity and meet time-to-market goals. IP-based design and verification methodology is essential but has put an additional verification burden on IP suppliers (internal and external). IP suppliers need to ensure that their IP is exhaustively verified and SoC Integrators need to ensure that al... » read more

Emulation Uses Increase


For more than two decades, [getkc id="30" comment="emulation"] was a technology in search of a market. While on paper it has always made sense to speed up simulation, using hardware acceleration was so pricey that few companies could justify the cost. Fast-forward to today and emulation is a major contributor to the bottom line at all of the Big Three [getkc id="7" kc_name="EDA"] companies. ... » read more

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