tag: formal verification

Tools And Flows In 2015
By Brian Bailey - 29 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

Tech Talk: Formal Discussion
By Brian Bailey - 28 Jan, 2015 - Comments: 0

Pratik Mahajan, senior R&D manager for verification at Synopsys, talks about how to use simulation plus formal verification. [youtube vid=TjO8up0nPGg] » read more

Problems Lurk In SoC Boundaries
By Brian Bailey - 04 Dec, 2014 - Comments: 0

Interfaces always have been a problem, because only rarely does anyone have responsibility for them. Responsibilities generally are tied to functional blocks with the prevailing notion that if all blocks do the right thing, they will also behave correctly when brought together. Design teams that believe this eventually find out the fallacy of this assumption. To make matters worse, these are of... » read more

Tech Talk: Formal Practices
By Brian Bailey - 24 Nov, 2014 - Comments: 0

[getentity id="22147" comment="Oski Technology"] president and CEO [getperson id="11074" comment="Vigyan Singhal"] defines [getkc id="33" comment="formal verification"], where to start, and how and when to use it. [youtube vid=pxoSWtb4xIw] » read more

A Formally Free Lunch
By Brian Bailey - 05 Nov, 2014 - Comments: 0

I am sure many of you can remember the successful events staged by [getperson id="11679" p_name="Eric Hennenhofer"], founder and CEO of [getentity id="22813" comment="Obsidian Software"]. While neither his name nor that of his company may be on the tip of your tongue, DVClub might ring a few more bells. He started it so that he could have a place to meet fellow engineers while enjoying a free l... » read more

Tech Talk: Formal Verification
By Brian Bailey - 03 Nov, 2014 - Comments: 0

Praveen Tiwari, senior R&D manager for verification at Synopsys, talks with Semiconductor Engineering about when to use formal verification, why it isn't limited to small parts of the design, how to reduce complexity, bounded proofs, and bug hunting. [youtube vid=v8CoIAWU1XA] » read more

Executive Insight: Prakash Narain
By Ed Sperling - 27 May, 2014 - Comments: 0

SE: What’s your biggest concern? Narain: We are a smaller company, and ultimately we compete on the basis of the quality of the solutions we provide to customers. What’s the value proposition? How many X better will our solution be compared to the existing solutions that are in deployed in the market? You make a projection about it in your mind, and you make investments, and until they�... » read more

The Assertion Conundrum
By Ann Mutschler - 22 May, 2014 - Comments: 2

It is well documented and widely agreed that assertions can provide a tremendous benefit to design and verification teams by reducing and even eliminating debug – but their use is still not ubiquitous. Part of the reason is that assertions cannot be picked up casually, noted David Larson, director of verification at [getentity id="22150" e_name="Synapse Design"]. “This is because asserti... » read more

Is Formal Ready To Displace Simulation?
By Brian Bailey - 21 May, 2014 - Comments: 2

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In part two, the panel focused on the subject of coverage and the ways in which formal coverage can be combined with simulation. In this segment we start exploring the impact that sequential equi... » read more

Does Formal Have You Covered?
By Brian Bailey - 24 Apr, 2014 - Comments: 1

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In this segment we start exploring those difficulties in more detail and the progress made with integrated coverage. Participating in the panel were Pete Hardee, director of product management fo... » read more

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