tag: formal verification

A Formally Free Lunch
By Brian Bailey - 05 Nov, 2014 - Comments: 0

I am sure many of you can remember the successful events staged by [getperson id="11679" p_name="Eric Hennenhofer"], founder and CEO of [getentity id="22813" comment="Obsidian Software"]. While neither his name nor that of his company may be on the tip of your tongue, DVClub might ring a few more bells. He started it so that he could have a place to meet fellow engineers while enjoying a free l... » read more

Tech Talk: Formal Verification
By Brian Bailey - 03 Nov, 2014 - Comments: 0

Praveen Tiwari, senior R&D manager for verification at Synopsys, talks with Semiconductor Engineering about when to use formal verification, why it isn't limited to small parts of the design, how to reduce complexity, bounded proofs, and bug hunting. [youtube vid=v8CoIAWU1XA] » read more

Executive Insight: Prakash Narain
By Ed Sperling - 27 May, 2014 - Comments: 0

SE: What’s your biggest concern? Narain: We are a smaller company, and ultimately we compete on the basis of the quality of the solutions we provide to customers. What’s the value proposition? How many X better will our solution be compared to the existing solutions that are in deployed in the market? You make a projection about it in your mind, and you make investments, and until they�... » read more

The Assertion Conundrum
By Ann Mutschler - 22 May, 2014 - Comments: 2

It is well documented and widely agreed that assertions can provide a tremendous benefit to design and verification teams by reducing and even eliminating debug – but their use is still not ubiquitous. Part of the reason is that assertions cannot be picked up casually, noted David Larson, director of verification at [getentity id="22150" e_name="Synapse Design"]. “This is because asserti... » read more

Is Formal Ready To Displace Simulation?
By Brian Bailey - 21 May, 2014 - Comments: 2

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In part two, the panel focused on the subject of coverage and the ways in which formal coverage can be combined with simulation. In this segment we start exploring the impact that sequential equi... » read more

Does Formal Have You Covered?
By Brian Bailey - 24 Apr, 2014 - Comments: 1

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In this segment we start exploring those difficulties in more detail and the progress made with integrated coverage. Participating in the panel were Pete Hardee, director of product management fo... » read more

Blog Review: April 9
By Ed Sperling - 09 Apr, 2014 - Comments: 0

Mentor’s Colin Walls discovered an interesting video of the software programming learning process—a teacher responding literally to commands from his students on how to make a jam sandwich. It’s harder than it looks. Cadence’s Brian Fuller captures a speech by his colleague, Sanjiv Taneja, about the need for a comprehensive verification approach and smart IP reuse. The overriding th... » read more

Post-Silicon Validation Using Formal Analysis
By Various Writers - 09 Apr, 2014 - Comments: 0

Verifying the current generation of complex SoCs requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employ... » read more

Tech Talk: Debugging IP
By Ed Sperling - 03 Apr, 2014 - Comments: 0

Just because IP is standard doesn't mean it will function as expected in a complex SoC. Ravindra Aneja, senior technical marketing manager at Atrenta, looks at what needs to be done to make sure everything works together. [youtube vid=wlDabbrF2zU] » read more

Formal Is Set To Overtake Simulation
By Brian Bailey - 27 Mar, 2014 - Comments: 4

There has been a significant psychology change in the area of formal verification over the past couple of years. It’s no longer considered a fringe technology, and it’s no longer considered difficult to use. In fact, it has become a necessary part of the verification process. Semiconductor Engineering sat down with a panel of experts to find out what caused this change and what more we c... » read more

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