tag: formal verification

Jasper Security Path Verification
By Various Writers - 10 Oct, 2013 - Comments: 0

Security path verification is the ability to verify the lack of existence of functional paths touching secure areas of a design. The Jasper security verification technology used in security path verification is based on path sensitization technology, which is used to find paths propagating data to and from secure areas. The Jasper technology can be used to verify requirements that are not exp... » read more

How Secure Is Your Design?
By Joseph Hupcey III - 10 Oct, 2013 - Comments: 0

Once upon a time, secure hardware was only needed for mil-aero and banking systems. Today, numerous industrial and consumer applications require special hardware to protect data required for digital rights management, electronic wallets, private encryption keys, or medical information. Current methodologies to verify that such hardware is impervious to attack and/or the data within remains s... » read more

Equivalence Checking
By Joseph Hupcey III - 12 Sep, 2013 - Comments: 0

Everyone is consumed by power these days. The less power our devices use, the better—the longer our batteries will last, the more applications we can use simultaneously, the less HVAC capacity is required by the data center, etc. Clock-gating is one widely used technique to save power in ASIC designs. However, clock gating can significantly impact the structural and behavioral elements of the... » read more

Delicate Balance
By Joseph Hupcey III - 08 Aug, 2013 - Comments: 0

By Joe Hupcey III It’s not surprising that power optimization is a critical part of today’s complex designs. Unbeknownst to most consumers is an underlying methodology that every design engineer must follow to make sure a consumer device meets the power requirements of the consumer—even if the consumer doesn’t realize they’re demanding it. The situation in industrial products, suc... » read more

Verifying Security Aspects Of SoC Designs
By Various Writers - 08 Aug, 2013 - Comments: 0

This paper presents Jasper technology and methodology to verify the robustness of secure data access and the absence of functional paths touching secure areas of a design. Recently, we have seen an increasing demand in industrial hardware design to verify security information. Complex system-on-chips, such as those for cell phones, game consoles, and servers contain secure information. And it i... » read more

Where Should I Use Formal Functional Verification?
By Various Writers - 11 Jul, 2013 - Comments: 0

With innovations in formal technologies and methodology, the benefits of formal functional verification apply in many more areas. Although a generic awareness of where formal functional verification applies is useful, understanding the "what" and the "why" leads to greater success. Clearly, if we understand the characteristics of areas with high formal applicability, we can identify not only wh... » read more

The New Verification Landscape
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler Verification technologies and tools have never been more sophisticated. But putting together a methodology is more than just putting tools together. It starts with trying to get a handle on the complexity, knowing what to test, how to test and when. “UVM was standardized and people have been working to adopt that which has been generally a positive,” said Steve Ba... » read more

Executive Briefing: Formal Attire
By Ed Sperling - 06 Jun, 2013 - Comments: 0

Kathryn Kranen, CEO of Jasper Design Automation, talks with Low Power-High-Performance Engineering about formal verification, where the pain points are in SoC design, and why there is still life left in Moore's Law. [youtube vid=x4jlo6_RRqw] » read more

Shifts In Verification
By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Verifying an SoC requires a holistic view of the system, and engineering teams use a number of tools to reach a high degree of confidence in the coverage. But how and when to use those tools is in flux as engineering teams wrestle with increasing complexity at every level of the design, and a skyrocketing increase in the challenge of verifying it. There are no ... » read more

Is This The Era Of Automatic Formal Checks For Verification?
By Graham Bell - 28 Feb, 2013 - Comments: 0

I was thinking about the above question and recalled something IBM would repeat annually back in the late 1980s about its OS/2 replacement for MS-DOS. “This is the year of OS/2!” they would shout. But the marketplace wasn’t listening. As one buddy of mine liked to say, it was only half of an operating system (O.S./2). In the last nine months, my company, Real Intent, along with our com... » read more

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