tag: formal verification

User Case Study
By Joseph Hupcey III - 08 Nov, 2013 - Comments: 0

In prior articles I’ve written in general terms of about formally verifying the impact of adding low power control circuitry with Jasper’s Low Power Verification App. At the recent Jasper User’s Group meeting on Oct. 22, a real world case study of this app in action at STMicro’s R&D center in India was presented. Here are some highlights from this paper: DUT in question: an AR... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 04 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Start Verification Early To Avoid Pitfalls Later
By Ann Mutschler - 24 Oct, 2013 - Comments: 1

It is well understood – at least from a theoretical point of view – that design verification should start as early as possible. The reality is that that doesn’t always happen for a variety of reasons such as enormous time to market pressure, too many new features to add, lack of foresight and discipline among other things. But progress is being made. Harry Foster, chief scientist for v... » read more

Experts At The Table: Debug
By Ed Sperling - 18 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: The amount of IP is increasing and i... » read more

Jasper Security Path Verification
By Various Writers - 10 Oct, 2013 - Comments: 0

Security path verification is the ability to verify the lack of existence of functional paths touching secure areas of a design. The Jasper security verification technology used in security path verification is based on path sensitization technology, which is used to find paths propagating data to and from secure areas. The Jasper technology can be used to verify requirements that are not exp... » read more

How Secure Is Your Design?
By Joseph Hupcey III - 10 Oct, 2013 - Comments: 0

Once upon a time, secure hardware was only needed for mil-aero and banking systems. Today, numerous industrial and consumer applications require special hardware to protect data required for digital rights management, electronic wallets, private encryption keys, or medical information. Current methodologies to verify that such hardware is impervious to attack and/or the data within remains s... » read more

Equivalence Checking
By Joseph Hupcey III - 12 Sep, 2013 - Comments: 0

Everyone is consumed by power these days. The less power our devices use, the better—the longer our batteries will last, the more applications we can use simultaneously, the less HVAC capacity is required by the data center, etc. Clock-gating is one widely used technique to save power in ASIC designs. However, clock gating can significantly impact the structural and behavioral elements of the... » read more

Delicate Balance
By Joseph Hupcey III - 08 Aug, 2013 - Comments: 0

By Joe Hupcey III It’s not surprising that power optimization is a critical part of today’s complex designs. Unbeknownst to most consumers is an underlying methodology that every design engineer must follow to make sure a consumer device meets the power requirements of the consumer—even if the consumer doesn’t realize they’re demanding it. The situation in industrial products, suc... » read more

Verifying Security Aspects Of SoC Designs
By Various Writers - 08 Aug, 2013 - Comments: 0

This paper presents Jasper technology and methodology to verify the robustness of secure data access and the absence of functional paths touching secure areas of a design. Recently, we have seen an increasing demand in industrial hardware design to verify security information. Complex system-on-chips, such as those for cell phones, game consoles, and servers contain secure information. And it i... » read more

Where Should I Use Formal Functional Verification?
By Various Writers - 11 Jul, 2013 - Comments: 0

With innovations in formal technologies and methodology, the benefits of formal functional verification apply in many more areas. Although a generic awareness of where formal functional verification applies is useful, understanding the "what" and the "why" leads to greater success. Clearly, if we understand the characteristics of areas with high formal applicability, we can identify not only wh... » read more

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