Verification Specialists And Generalists

By Dave Kelf - 22 Nov, 2016 - Comments: 0

Step into any weekly status update meeting where the topic is chip design verification, especially if formal verification is on the agenda, and it’s clear the verification department is moving much like traditional corporate environments. That is, there are generalists with loads of knowledge about many different verification tools and techniques and then there are specialists or experts who ... » read more

DVCon Europe: 2 Days Of Verification Presentations To Enthusiastic Attendees

By Dave Kelf - 27 Oct, 2016 - Comments: 0

Design verification was on full display last week in Munich, Germany, as DVCon Europe offered two full days of more than 30 sessions. Attendees could choose from 16 tutorials, two panels, three keynotes and 16 technical presentations or wander through a small but active exhibit floor, with exhibitors that included OneSpin. The conference for engineers by engineers is meant to be educational,... » read more

Using Formal Verification To Prevent Catastrophic Security Breaches

By Dave Kelf - 29 Sep, 2016 - Comments: 0

The news of last week’s Yahoo hack that affected 500-million or so users sent shock waves of anxiety far and wide. It’s not clear yet how the massive data breach occurred or through what means the hackers accessed the network. It could be the chips that drive the network, often vulnerable to attacks on their operational integrity. It’s no surprise, then, that semiconductor companies ar... » read more

Gaps In The Verification Flow

By Brian Bailey - 29 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

Customizable Apps – Avoiding The Pitfalls Of EDA Frameworks

By Dave Kelf - 25 Aug, 2016 - Comments: 0

For those of us involved with EDA tools in the late '80s and early '90s, the word “frameworks” brings back memories of rigid methodology and use models, coupled with CAD complexity. Cadence and Mentor, among others, proposed the EDA framework as a mechanism to provide design revision management coupled with tool flow control (I can already imagine your eyes glazing over). For some situat... » read more

Formal Has Its Day

By Dave Kelf - 28 Jul, 2016 - Comments: 0

As new technologies receive more mainstream attention, it is common for the experts in the area to provide a critical mass of enthusiasm. Formal is in this mode with multiple meetings throughout the year and around the globe. Perhaps one of the most successful of these is the annual Formal Day event put on by Test & Verification Solutions (TVS) based in the UK. This live and online event is... » read more

Can Verification Meet In The Middle?

By Brian Bailey - 20 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss these issues with; Stan Sokorac, senior principal design engineer for [getentity id="22186" comment="ARM"]; Frank Schirrmeister, senior group director for product marketing for the system development suite of [getentity id="22032" e_name="Cadence"]; Harry Foster, chief verification scientist at [getentity id="22017" e_name="Mentor Graphics"], Bernie... » read more

Verification Engine Disconnects

By Ed Sperling - 06 Jul, 2016 - Comments: 0

Moving verification data seamlessly between emulation, simulation, FPGA prototyping and formal verification engines may be possible on paper, but it is proving more difficult to implement in the real world. [getkc id="10" kc_name="Verification"] still consumes the most time and money in the design process. And while the amount of time spent on verification in complex designs has held relativ... » read more

The Secret To Good Comedy And SystemC Code Verification… Timing!

By Dave Kelf - 30 Jun, 2016 - Comments: 0

The High-Level Synthesis (HLS) of algorithmic code, usually written in SystemC, is steadily gaining ground. However, the verification of this code is still a somewhat mixed-up, ad-hoc process. The situation is improving as new techniques are applied, but it is clear that in-the-trenches evaluation of these solutions on real projects is more important right now than grand visions missing substan... » read more

The Early Bird Catches The Bug Using Formal

By Dave Kelf - 28 Apr, 2016 - Comments: 0

It has been suggested that formal might replace simulation, at least in some parts of the design flow. Not likely! The question is, how can formal be layered on top of simulation flows to improve coverage and schedule? The way formal is being used at the larger semiconductor companies is evolving. In many of these companies a small team of hardcore formal experts are employed across differen... » read more

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tag: formal

Verification Specialists And Generalists

DVCon Europe: 2 Days Of Verification Presentations To Enthusiastic Attendees

Using Formal Verification To Prevent Catastrophic Security Breaches

Gaps In The Verification Flow

Customizable Apps – Avoiding The Pitfalls Of EDA Frameworks

Formal Has Its Day

Can Verification Meet In The Middle?

Verification Engine Disconnects

The Secret To Good Comedy And SystemC Code Verification… Timing!

The Early Bird Catches The Bug Using Formal

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