DVCon Europe: 2 Days Of Verification Presentations To Enthusiastic Attendees

Verification challenges are at the heart of this conference.


Design verification was on full display last week in Munich, Germany, as DVCon Europe offered two full days of more than 30 sessions. Attendees could choose from 16 tutorials, two panels, three keynotes and 16 technical presentations or wander through a small but active exhibit floor, with exhibitors that included OneSpin.

The conference for engineers by engineers is meant to be educational, practical and application-oriented with an emphasis on design and verification of electronic systems and ICs. It succeeded. Attendance was up 20% over last year, a number to make any other conference organizer envious.

An obvious reason for the increase is the growing chip design challenges, and DVCon Europe covered many of them. We heard two keynotes describing some of these challenges. Hobson Bullman from ARM described the design verification methodology and infrastructure solutions ARM implemented internally to deliver IP into its partner base that spans a wide variety of markets. NXP Semiconductors’ Juergen Weyer gave his audience a look at the road ahead for the securely connected, self-driving car with an in-depth examination of the technologies driving the autonomous vehicles revolution of the future, highlighting security, reliability and safety requirements.

As both Hobson and Juergen pointed out, verification tools aren’t nice to have. Rather, they are essential to get any electronics product to market, especially those with embedded software. Other presenters shared similar experiences on the practical use of EDA standards, languages and methodologies for design and verification, always fascinating and informative. As well, the European emphasis on mixed-signal, functional-safety and system-level design and variation was emphasized in the program. Attendees heard about a broad range of current design and verification topics, including SystemC methodology evolution, Universal Verification Methodology (UVM), portable stimulus, analog/mixed signal, low power, functional safety and high-reliability development.

Formal verification, OneSpin’s area of expertise, was widely discussed last week. Much like emulation, design verification groups are adopting formal for a variety of uses. Safety critical designs, in fact, lead the way in the application of formal methods for key design blocks with high-reliability characteristics. One tutorial provided practical and simple examples of formal verification’s strength in safety critical methodologies, and demonstrated how it makes the job of verification easier.

During Wednesday night’s gala dinner, Bob Smith of the ESD Alliance, a last-minute replacement keynote speaker, took a more global view of the semiconductor design ecosystem than design verification. He acknowledged we’re evolving from a chip-centric focus to a system-centric focus, something driven by European companies.

One often-overlooked aspect of a conference is the opportunity to network informally with colleagues and business associates to exchange information, and DVCon Europe attendees used the occasion to connect.

The DVCon franchise expanded from the yearly DVCon in the U.S. to Europe and India three years ago. It’s moving to China for the first DVCon China April 19, 2017. If it’s at all like the DVCons in the U.S., Europe and India, it will be a hit. The original DVCon U.S. will be held February 27-March 2, 2017 at the DoubleTree Hotel in San Jose, Calif.

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