tag: formal

Tackling Functional Correctness, Safety, Trust And Security
By Rob van Blommestein - 29 Sep, 2020 - Comments: 0

We’re six months into the pandemic, and it looks like in-person conferences are becoming a distant memory and that virtual conferences are now becoming routine. It used to be that traveling to a conference (sometimes long distances) was the only way to be able to attend technical presentations and learn about the latest technologies and methodologies, and that was only if you received permiss... » read more

Faster Formal Verification Closure For Datapaths In AI Designs
By Neelabja Dutta - 04 Jun, 2020 - Comments: 0

In recent years, many longstanding assumptions about formal verification have been rendered obsolete by ever-improving technology. Applications such as connectivity checking have shown that formal can work on large system-on-chip (SoC) designs, not just small blocks. Standard SystemVerilog Assertions (SVA) have eliminated the need to learn an abstruse mathematical language for each new formal t... » read more

FPGA Equivalence Checking For A Nuclear Safety Controller
By Rob van Blommestein - 28 May, 2020 - Comments: 0

Every chip development team wants to find and fix all the bugs they possibly can in pre-silicon verification. Turning a chip to fix issues found in the bring-up lab incurs high costs and product delays; bugs found in the field are even more expensive to repair. But for some applications, including military/aerospace, implanted medical devices, and autonomous vehicles, the consequences of a faul... » read more

The Seven Steps Of Formal Signoff
By Iain Singleton - 28 May, 2020 - Comments: 0

“Signoff” may be the most exciting—and frightening—word in semiconductor development. After many months, or even years of team effort, committing a design to silicon fabrication is indeed an exciting and rewarding event. But, there’s often significant anxiety involved as well – if any missed issues result in having to “turn” the chip, the increased costs and time-to-market delay... » read more

Access To Verification Knowledge While Remote Working
By Rob van Blommestein - 23 Apr, 2020 - Comments: 0

As someone who is used to working from home, the recent global events haven’t had as much of an impact on my ability to keep productive. Our team at OneSpin is very adept with remote-working relationships as many of us reside all over the world. Having said this, we recognize that not everyone or every company shares in this situation. Working from home can create specific challenges when ... » read more

GapFree Processor Verification
By Tom Anderson - 26 Mar, 2020 - Comments: 0

Not so long ago, many semiconductor and system suppliers developed their own processors, often with unique features geared toward specific target applications. Although this innovation has continued for specialty processors such as digital signal-processing (DSP) engines and graphics processing units (GPUs), central processing units (CPUs) largely turned into a two-contestant race between x86 a... » read more

Verification Planning And Management With Formal
By Tom Anderson - 30 Jan, 2020 - Comments: 0

Over the last twenty years, formal verification has grown from a niche technology practiced only by specialists to an essential part of mainstream chip development. Along the way, several advances were needed to make wider adoption of formal feasible. These included the standardization of assertion languages, enhanced formal engine performance and capacity, better debug capabilities, and pushbu... » read more

Functional Safety Verification For AV SoC Designs Accelerated With Advanced Tools
By Jacob Wiltgen - 05 Dec, 2019 - Comments: 0

Autonomous vehicles (AVs) will be the culmination of dozens of highly complex systems, incorporating state-of-the-art technologies in electronics hardware, sensors, software, and more. Conceiving and designing these systems is certain to be one of the greatest challenges for today’s engineers. The only greater challenge will be convincing a wary public that these automated systems are safer d... » read more

Three Steps To Complete Reset Behavior Verification
By Chris Kwok - 14 Nov, 2019 - Comments: 0

By Chris Kwok, Priya Viswanathan, and Ping Yeung Reset architectures are notoriously complex and difficult to verify. Today’s SoCs contain highly complex reset distributions and synchronization circuitry. Often, reset trees can be larger than clock trees and have many of the same potential issues. Verifying that a design can be correctly reset under all modes of operation presents signi... » read more

Scaling Formal Connectivity Checking To Multi-Billion-Gate SoCs With Specification Automation
By OneSpin Solutions - 23 Oct, 2019 - Comments: 0

Connectivity checking is a popular formal verification application. Formal tools can automatically generate assertions using a specification table as input and prove them exhaustively. Simulation-based verification, on the other hand, requires significantly more effort while providing a fraction of the coverage. However, chip complexity is rapidly increasing. ASICs and FPGAs for heterogeneous c... » read more

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