Outlook 2016 – The year of Horizontal and Vertical Flow Integration

By Frank Schirrmeister - 22 Dec, 2015 - Comments: 0

As 2015 comes to an end rapidly, the key question becomes what the next year will bring. Last year around this time, in my blog “The Next Big Shift In Verification”, I talked about software-driven verification as the next era of verification that follows the eras of directed testing and High-level Verification Language (HVL) driven verification. I also had referred to our System Development... » read more

Who’s Profiting From Complexity

By Ed Sperling - 21 Dec, 2015 - Comments: 0

Tool vendors' profits increasingly are coming from segments that performed relatively poorly in the past, reflecting both a rise in complexity in designing chips and big improvements in the tools themselves. The impacts of power, memory congestion, advanced-node effects such as process variation, [getkc id="160" kc_name="electromigration"] and RC delay in [getkc id="36" kc_name="interconnect... » read more

Hardware Models For Software

By Brian Bailey - 24 Nov, 2015 - Comments: 1

Shift left, while a relatively new term, has become important in all parts of the SoC design flow, but its impacts are wide ranging and many still ill defined. It basically means that tasks have to be started earlier than in the past because more accuracy is required from tasks that are further down in the flow in order to make better predictions. It also implies that more steps are performed c... » read more

Hybrid Emulation Gets More Hybrid

By Ed Sperling - 29 Oct, 2015 - Comments: 0

Rising chip complexity is creating a booming emulation business, as chipmakers working at advanced nodes turn to bigger iron to get chips out the door on time. What started as a "shift lift"—doing more things earlier in the design cycle—is evolving into a more complex mix of hardware-accelerated verification for both hardware and software. There are even some new forays into power explor... » read more

High-Speed Systems Need High-Speed Parts For Prototyping

By Rich Wawrzyniak - 12 Oct, 2015 - Comments: 0

One of the ironies of prototyping for high-speed system design using FPGAs is that in the past most FPGAs did not run at the speeds required by the end system. Many of these FPGAs today have high speed SerDes channels used for communicating with other elements of the system at close to the speeds specified by the designer. Unfortunately most of the FPGAs used for the prototyping phase of the sy... » read more

A Word About FPGA-Based Prototyping

By Tom De Schutter - 24 Sep, 2015 - Comments: 0

With software now driving the main capabilities of embedded devices, prototyping has taken the spotlight in SoC design. This is turning a once-hardware-centric electronics supply chain upside down. To cope with this new reality, companies are embracing both virtual and physical prototyping technologies. Physical prototyping, also known as FPGA-based prototyping, is an important piece of an e... » read more

Wrong Verification Revolution Offered

By Brian Bailey - 25 Jun, 2015 - Comments: 0

SoC design traditionally has been an ad-hoc process, with implementation occurring at the register transfer level. This is where verification starts, and after the blocks have been verified, it becomes an iterative process of integration and verification that continues until the complete system has been assembled. But today, this methodology has at least two major problems, which were addres... » read more

Towards A Metric To Measure Verification Computing Efficiency

By Frank Schirrmeister - 25 Jun, 2015 - Comments: 1

Thinking back about DAC 2015 in San Francisco earlier this month, I am happy that at least some of my predictions came true—there was clearly a trend towards making verification smarter. However, one thing struck me while hearing all the discussions on connecting engines is what Jim Hogan called the continuum of verification engines (COVE)—and what we at Cadence call the system development ... » read more

Tech Talk: Power Tools

By Ed Sperling - 27 May, 2015 - Comments: 0

At 200 million gates, using standard tools for power will add weeks to the semiconductor design process. Vijay Chobisa, product marketing manager at Mentor Graphics, talks with Semiconductor Engineering about where the problems are and how to solve them. [youtube vid=w7yEdtaIb9A] » read more

A Fireside Chat With Imagination On Hardware-Assisted Development And Emulation

By Frank Schirrmeister - 13 May, 2015 - Comments: 0

During one of my trips to Europe I was able to sit down with Colin McKellar, senior director of hardware engineering at Imagination Technologies. He is my main contact for all things verification at Imagination. Imagination’s product challenges include maintaining the level of quality of their IP products within shorter timelines and dealing with integration of their IP into more complex c... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

tag: FPGA prototyping