tag: Fraunhofer IIS EAS

Silo Busting In The Design Flow
By Brian Bailey - 24 Nov, 2020 - Comments: 0

An increasing number of dependencies in system design are forcing companies, people, tools, and flows to become more collaborative. Design and EDA companies must adapt to this new reality because it has become impossible for anyone to do it all by themselves. Moreover, what happens in manufacturing and packaging needs to be considered up front, and what gets designed in the design phase may ... » read more

Brute-Force Analysis Not Keeping Up With IC Complexity
By Brian Bailey - 24 Nov, 2020 - Comments: 0

Much of the current design and verification flow was built on brute force analysis, a simple and direct approach. But that approach rarely scales, and as designs become larger and the number of interdependencies increases, ensuring the design always operates within spec is becoming a monumental task. Unless design teams want to keep adding increasing amounts of margin, they have to locate th... » read more

Electronics For Quantum Communications
By Andy Heinig - 12 Nov, 2020 - Comments: 1

Our secure digital communications so far have functioned on the principle of key-based encryption. This involves generating a key of appropriate length, which is then used to encrypt the data. Because distributing the keys is difficult, the keys are reused rather than regularly generating new ones. The regular use of the keys opens up the encryption process to attacks by mathematical methods... » read more

Dealing With Sub-Threshold Variation
By Bryon Moyer - 12 Nov, 2020 - Comments: 0

Chipmakers are pushing into sub-threshold operation in an effort to prolong battery life and reduce energy costs, adding a whole new set of challenges for design teams. While process and environmental variation long have been concerns for advanced silicon process nodes, most designs operate in the standard “super-threshold” regime. Sub-threshold designs, in contrast, have unique variatio... » read more

Artificial Intelligence For Sustainable And Energy Efficient Buildings
By Fraunhofer IIS/EAS - 11 Nov, 2020 - Comments: 0

According to the goals of Europe’s green deal missions, the continent strives for becoming carbon neutral by 2050. Since buildings are a major contributor to the overall consumption of energy, improving their energy efficiency can be a key to a more sustainable and greener Europe. On the way towards zero-emission buildings, several challenges have to be met: In modern energy systems, several ... » read more

Increase In Analog Problems
By Brian Bailey - 19 Oct, 2020 - Comments: 6

Analog and mixed signal design has always been tough, but a resent survey suggests that the industry has seen significantly increased failures in the past year because the analog circuitry within an ASIC was out of tolerance. What is causing this spike in failures? Is it just a glitch in the data, or are these problems real? The answer is complicated, and to a large extent it depends heavily... » read more

Confusion Grows Over Packaging And Scaling
By Ann Mutschler - 15 Oct, 2020 - Comments: 0

The push toward both multi-chip packaging and continued scaling of digital logic is creating confusion about how to classify designs, what design tools work best, and how to best improve productivity and meet design objectives. While the goals of design teams remains the same — better performance, lower power, lower cost — the choices often involve tradeoffs between design budgets and ho... » read more

13-Gb/s Transmitter For Bunch Of Wires Chip-To-Chip Interface Standard
By Fraunhofer IIS/EAS - 14 Oct, 2020 - Comments: 0

Continuous downscaling of integrated circuits has reached a bottleneck. Technologies such as system in a package, multi-chip module and integration of chips on an active or passive interposer can further improve the system performance. Bunch of wires interface standard was recently introduced for chip to chip short interfaces within a package. This standard required both terminated and untermin... » read more

Analog Chip Layout: Creativity Vs. Deadlines
By Benjamin Prautsch - 10 Sep, 2020 - Comments: 0

The entire design of integrated circuits, from the specification onward, depends on successful validation by measurement of microchips. One key milestone in this process is the completion of the layout. However, the path to reach this point can be quite difficult as many iterations are usually required. It includes: Iterations with the customer to finalize the specification. Iteratio... » read more

Dealing With Device Aging At Advanced Nodes
By Ann Mutschler - 10 Sep, 2020 - Comments: 0

Premature aging of circuits is becoming troublesome at advanced nodes, where it increasingly is complicated by new market demands, more stress from heat, and tighter tolerances due to increased density and thinner dielectrics. In the past, aging and stress largely were separate challenges. Those lines are starting to blur for a number of reasons. Among them: In automotive, advanced-node... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy