tag: Fraunhofer IIS EAS

Defining And Improving AI Performance
By Brian Bailey - 12 Dec, 2019 - Comments: 2

Many companies are developing AI chips, both for training and for inference. Although getting the required functionality is important, many solutions will be judged by their performance characteristics. Performance can be measured in different ways, such as number of inferences per second or per watt. These figures are dependent on a lot of factors, not just the hardware architecture. The optim... » read more

5 Major Shifts In Automotive
By Ed Sperling - 11 Dec, 2019 - Comments: 1

Much of the automotive industry has begun repositioning and retrenching over the past few months, pushing back the projected rollout for fully autonomous vehicles and changing direction on power sources and technology used in the next-generation of electric vehicles. Taken together, these shifts mark a significant departure for traditional automakers, which find themselves playing catch-up t... » read more

Reducing Data At The Source
By Ed Sperling - 18 Nov, 2019 - Comments: 0

Jens Döge, group manager for image acquisition and processing in Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about how to slash the amount of data that needs to be sent to the cloud or edge for processing by focusing only on the regions of interest in an image, and how that reduces the cost of moving that data. » read more

Virtual System Development Platforms For Safeguarding Complex Microelectronic Systems
By Roland Jancke - 14 Nov, 2019 - Comments: 0

Electronic systems are rapidly becoming more complex. This impacts almost all domains in which electronics are used today — especially industrial applications, medical engineering, communications engineering and, of course, automotive applications. What's changed is the addition of huge numbers of sensors and actuators that interact with the environment, the local integration of highly co... » read more

Speeding Up 3D Design
By Brian Bailey - 14 Nov, 2019 - Comments: 0

2.5D and 3D designs have garnered a lot of attention recently, but when should these solutions be considered and what are the dangers associated with them? Each new packaging option trades off one set of constraints and problems for a different set, and in some cases the gains may not be worth it. For other applications, they have no choice. The tooling in place today makes it possible to de... » read more

Power Complexity On The Rise
By Ann Mutschler - 14 Nov, 2019 - Comments: 0

New chip architectures and custom applications are adding significant challenges to chip design and verification, and the problems are becoming much more complex as low power is added into the mix. Power always has been a consideration in design, but in the past it typically involved different power domains that were either on, off, or in some level of sleep mode. As hardware architectures s... » read more

Revving Up For Edge Computing
By Ed Sperling - 07 Nov, 2019 - Comments: 1

The edge is beginning to take shape as a way of limiting the amount of data that needs to be pushed up to the cloud for processing, setting the stage for a massive shift in compute architectures and a race among chipmakers for a stake in a new and highly lucrative market. So far, it's not clear which architectures will win, or how and where data will be partitioned between what needs to be p... » read more

IoT For Building Energy Systems In Zero-Emission Buildings
By Dirk Mayer - 10 Oct, 2019 - Comments: 0

By Dirk Mayer and Olaf Enge-Rosenblatt How can buildings contribute to a significant reduction in global primary energy consumption? Due to the global trend toward reducing CO2 emissions and resource conservation, the demands are increasing with regard to the efficiency of heating, ventilation and air-conditioning (HVAC) systems operated in buildings. In conflict with calls for fas... » read more

Using Emulators For Power/Performance Tradeoffs
By Ann Mutschler - 10 Oct, 2019 - Comments: 1

Emulation is becoming the tool of choice for power and performance tradeoffs, scaling to almost unlimited capacity for complex chips used in data centers, AI/ML systems and smart phones. While emulation has long been viewed as an important but expensive asset for chipmakers trying to verify and debug chips, it is now viewed as an essential component for design optimization and analysis much ... » read more

From Constraints to Tape-Out: Towards a Continuous AMS Design Flow
By Fraunhofer IIS/EAS - 10 Oct, 2019 - Comments: 0

Author(s): Krinke, Andreas; Horst, Tilman; Gläser, Georg; Grabmann, Martin; Markus, Tobias; Prautsch, Benjamin; Hatnik, Uwe; Lienig, Jens The effort in designing analog/mixed-signal (AMS) integrated circuits is characterized by the largely manual work involved in the design of analog cells and their integration into the overall circuit. This inequality in effort between analog and digital... » read more

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