tag: Fraunhofer IIS EAS

Memory On Logic: The Good And Bad
By Brian Bailey - 11 Apr, 2024 - Comments: 0

The chip industry is progressing rapidly toward 3D-ICs, but a simpler step has been shown to provide gains equivalent to a whole node advancement — extracting distributed memories and placing them on top of logic. Memory on logic significantly reduces the distance between logic and directly associated memory. This can increase performance by 22% and reduce power by 36%, according to one re... » read more

Using AI/ML To Minimize IR Drop
By Ann Mutschler - 11 Apr, 2024 - Comments: 1

IR drop is becoming a much bigger problem as technology nodes scale and more components are packed into advanced packages. This is partly a result of physics, but it's also the result of how the design flow is structured. In most cases, AI/ML can help. The underlying problem is that moving to advanced process nodes, and now 3D-ICs, is driving current densities higher, while the power envelop... » read more

Trusted Electronics: Current And Future Developments
By Roland Jancke - 11 Apr, 2024 - Comments: 0

In today’s world, we encounter electronics increasingly as complex hardware/software systems, such as those in vehicles, machines, and communication devices. These systems are characterized by dramatic increases in functionality in areas like environment sensing, stages of autonomy, and the installation of future updates. Developing and manufacturing such electronic systems today requires glo... » read more

Low-Power Relaxation Oscillator With Temperature-Compensated Thyristor Decision Elements
By Fraunhofer IIS/EAS - 10 Apr, 2024 - Comments: 0

This paper presents a low-power 140 kHz relaxation oscillator (ROSC) for low-frequency clock generators and timers. In voltage-mode ROSCs, unavoidable shunt current consumption results from voltage slewing at the integration capacitor. The proposed circuit employs CMOS thyristor-based decision elements which effectively reduce shunt currents by exploiting internal positive feedback. A complemen... » read more

NoCs In 3D Space
By Brian Bailey - 03 Apr, 2024 - Comments: 0

A network on chip (NoC) has become an essential piece of technology that enables the complexity of chips to keep growing, but when designs go 3D, or when third-party chiplets become pervasive, it's not clear how NoCs will evolve or what the impact will be on chiplet architectures. A NoC enables data to move between heterogeneous computing elements, while at the same time minimizing the resou... » read more

What’s Missing In 2.5D EDA Tools
By Brian Bailey - 28 Mar, 2024 - Comments: 0

Gaps in EDA tool chains for 2.5D designs are limiting the adoption of this advanced packaging approach, which so far has been largely confined to high-performance computing. But as the rest of the chip industry begins migrating toward advanced packaging and chiplets, the EDA industry is starting to change direction. There are learning periods with all new technologies, and 2.5D advanced pack... » read more

Interconnects Essential To Heterogeneous Integration
By Karen Heyman - 28 Mar, 2024 - Comments: 0

Designing and manufacturing interconnects is becoming more complex, and more critical to device reliability, as the chip industry shifts from monolithic planar dies to collections of chips and chiplets in a package. What was once as simple as laying down a copper trace has evolved into tens of thousands of microbumps, hybrid bonds, through-silicon vias (TSVs), and even junctions for optical ... » read more

Current And Future Challenges For An Open Chiplet Ecosystem
By Andy Heinig - 14 Mar, 2024 - Comments: 0

There are currently a variety of ways to approach chiplet systems. One is to have a closed system in which a manufacturer develops all the components in-house and is also in charge of commissioning and overseeing assembly. In this scenario, everything is coordinated within that company and no standards are required. Another is to establish open chiplet systems. This approach taps a considera... » read more

Backside Power Delivery Adds New Thermal Concerns
By Karen Heyman - 14 Mar, 2024 - Comments: 0

As the semiconductor industry gears up for backside power delivery at the 2nm node, implementation of the technology requires a re-thinking of established design practices. While some EDA tools are already qualified, designers must acquaint themselves with new issues, including making place-and-route more thermal-aware and how to manage heat dissipation with less shielding and thinner substr... » read more

The Rising Price Of Power In Chips
By Ed Sperling - 14 Mar, 2024 - Comments: 0

Power is everything when it comes to processing and storing data, and much of it isn't good. Power-related issues, particularly heat, dominate chip and system designs today, and those issues are widening and multiplying. Transistor density has reached a point where these tiny digital switches are generating more heat than can be removed through traditional means. That may sound manageable e... » read more

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