tag: Fraunhofer IIS/EAS

Chiplets Taking Root As Silicon-Proven Hard IP
By Ann Mutschler - 09 Feb, 2023 - Comments: 0

Chiplets are all the rage today, and for good reason. With the various ways to design a semiconductor-based system today, IP reuse via chiplets appears to be an effective and feasible solution, and a potentially low-cost alternative to shrinking everything to the latest process node. To enable faster time to market, common IP or technology that already has been silicon-proven can be utilized... » read more

Growing System Complexity Drives More IP Reuse
By Ann Mutschler - 12 Jan, 2023 - Comments: 1

IP reuse of both third-party and internal IP is growing, but it's also becoming more complex to manage. There is more IP being used, and more systems into which it needs to be integrated, combined with other IP, and tracked throughout an organization. In some cases, this is an economic requirement. In others, designs are so complex that engineering teams need to focus on where they will make... » read more

On The Reverse Breakdown Behavior Of GaAs PIN Diodes For High Power Applications
By Fraunhofer IIS/EAS - 11 Jan, 2023 - Comments: 0

In the field of power electronics, the compound semiconductors gallium nitride and silicon carbide are dominating the market. Due to its beneficial properties, gallium arsenide is gaining more and more importance. The aim is to manufacture devices based on gallium arsenide for use in power electronics with comparable or better properties, but at lower costs. In this work, a first GaAs PIN diode... » read more

Edge AI And Chiplets
By Andy Heinig - 08 Dec, 2022 - Comments: 0

In the near future, more edge artificial intelligence (AI) solutions will find their way into our lives. This will be especially true in the private sector for applications in the field of voice input and analysis of camera data, which will become well-established. These application areas require powerful AI hardware to be able to process the corresponding continuously accumulating data volumes... » read more

Improving Chip Efficiency, Reliability, And Adaptability
By Ed Sperling - 08 Dec, 2022 - Comments: 0

Peter Schneider, director of Fraunhofer Institute for Integrated Circuits' Engineering of Adaptive Systems Division, sat down with Semiconductor Engineering to talk about new models and approaches for ensuring the integrity and responsiveness of systems, and how this can be done within a given power budget and at various speeds. What follows are excerpts of that conversation. SE: Where are y... » read more

Holistic Die-to-Die Interface Design Methodology For 2.5-D Multi-Chip-Module Systems
By Fraunhofer IIS/EAS - 07 Dec, 2022 - Comments: 0

More than Moore technologies can be supported by system level diversification enabled by chiplet based integrated systems within multi-chip-modules (MCM) and silicon interposer based 2.5D systems. The division of large system-on-chip dies into smaller chiplets with different technology nodes specific to the chiplet application requirement enables the performance enhancement at system level whil... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Nov, 2022 - Comments: 0

Chip design Fraunhofer IIS/EAS implemented the Bunch of Wires (BoW) standard-based interface IP from the Open Compute Project (OCP) on Samsung's 5nm technology. The effort is intended to make chiplets more feasible for products with small and medium-sized production runs and determine the need for additional uniform standards in the future, such as for die-to-die bonding. “As part of t... » read more

Predictive Health Monitoring In Functional Safety
By Jens Michael Warmuth - 10 Nov, 2022 - Comments: 0

Functional safety first became a major issue for the semiconductor industry in 2011 with the introduction of the ISO 26262 standard for implementing functional safety in the automotive industry. Before that, functional safety had already been standardized in a general manner for all industries since the end of the 1990s in IEC 61508. However, in the field of industrial automation, where the IEC... » read more

Solving Thermal Coupling Issues In Complex Chips
By Ann Mutschler - 10 Nov, 2022 - Comments: 0

Rising chip and packaging complexity is causing a proportionate increase in thermal couplings, which can reduce performance, shorten the lifespan of chips, and impact overall reliability of chips and systems. Thermal coupling is essentially a junction between two devices, such as a chip and a package, or a transistor and a substrate, in which heat is transferred from one to the other. If not... » read more

Balancing Power And Heat In Advanced Chip Designs
By Karen Heyman - 10 Nov, 2022 - Comments: 1

Power and heat use to be someone else's problem. That's no longer the case, and the issues are spreading as more designs migrate to more advanced process nodes and different types of advanced packaging. There are a number of reasons for this shift. To begin with, there are shrinking wire diameters, thinner dielectrics, and thinner substrates. The scaling of wires requires more energy to driv... » read more

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