Gate-All-Around: TCAD and DTCO Approach To Evaluate Power and Performance (imec, et al.)


A new technical paper titled "Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: a TCAD-DTCO Study at 90 nm & 120 nm Cell Height" was published by imec, Huawei Technologies and Global TCAD Solutions. Abstract "This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power an... » read more

Models for Both Strained and Unstrained GAA FETs Using Neural Networks


A new technical paper titled "Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach" was published by researchers at Hanyang University and Alsemy Inc. Abstract "Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D... » read more

Highly Stacked Nanowire FETs To Enhance Drive Current And Transistor Density


A technical paper titled “Fabrication and performance of highly stacked GeSi nanowire field effect transistors” was published by researchers at National Taiwan University. Abstract: "Horizontal gate-all-around field effect transistors (GAAFETs) are used to replace FinFETs due to their good electrostatics and short channel control. Highly stacked nanowire channels are widely believed to en... » read more

Nanosheet GAAFETs: Compact Modeling (Politecnico di Torino)


A technical paper titled “NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance” was published by researchers at Politecnico di Torino. Abstract: "NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as ... » read more

Vertical Nanowire Gate-All-Around FETs based on the GeSn-Material System Grown on Si


A new technical paper titled "Vertical GeSn nanowire MOSFETs for CMOS beyond silicon" was published by researchers at Peter Grünberg Institute 9, JARA, RWTH Aachen University, CEA, LETI, University of Grenoble Alpes, University of Leeds, and IHP. "Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transcon... » read more

Innovations in Device Design of The Gate-All-Around (GAA) Nanosheet FETs (IBM Research)


A technical paper titled "A Review of the Gate-All-Around Nanosheet FET Process Opportunities" was published by researchers at IBM Research Albany. Abstract: "In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed. These innovations span enablement of multiple threshold voltages and bottom dielectric isolation in addition to impact of channel... » read more

Epi SiGe Application Using METRION In-Line SIMS System


The epitaxial process is a well-established deposition technique in semiconductor fabrication because it enables the ability to achieve much higher doping concentrations than can be obtained via ion implantation. As we move toward <5nm technology, a key process for enabling gate-all-around FET (GAAFET) is the stacked multi-lattice of Silicon (Si) and Silicon-germanium (SiGe) epi process for ... » read more

Review Paper: Negative Capacitance GAA-FET


A new technical paper titled "Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review" by researchers at PKU-HKUST Shenzhen-Hong Kong Institution and Shenzhen Institute of Peking University. "The novel device structure of negative capacitance gate all around field effect transistor (NC GAA-FET) can combine both the advantages of GAA-FET and NC-FET, and ... » read more