Chip Industry’s Technical Paper Roundup: October 31

New technical papers added to Semiconductor Engineering’s library this week. [table id=159 /] More Reading Technical Paper Library home » read more

Predicting Defect Properties In Semiconductors With Graph Neural Networks

A technical paper titled “Accelerating Defect Predictions in Semiconductors Using Graph Neural Networks” was published by researchers at Purdue University, Indian Institute of Technology (IIT) Madras, GE Research, and National Institute of Standards and Technology (NIST). Abstract: "Here, we develop a framework for the prediction and screening of native defects and functional impurities i... » read more

Blog Review: July 6

Synopsys' Mike Gianfagna looks at how the data center paradigm has shifted in the last ten years with an exponential increase in the amount of data demanding new approaches to storage that rely on distributed networks. Cadence's Frank Schirrmeister explains multidisciplinary design analysis and optimization, or MDAO, and how it is being combined with machine learning models to enhance classi... » read more