Chip Industry’s Technical Paper Roundup: October 31

Microelectronics packaging ecosystem; 2D transistors; chip defect predictions using GNNs; RISC-V system with HW accelerated task scheduling; auto security testing; pentalayer rhombohedral graphene; optical communication receivers; noisy quantum processors.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
US Microelectronics Packaging Ecosystem: Challenges and Opportunities University of Florida, University of Miami, and Skywater Technology Foundry
Process integration and future outlook of 2D transistors Intel Corporation
Accelerating Defect Predictions in Semiconductors Using Graph Neural Networks Purdue University, IIT Madras, GE Research, and NIST
Enabling HW-based Task Scheduling in Large Multicore Architectures Barcelona Supercomputing Center, University of Campinas, University of Sao Paulo, and Arteris
Applying Security Testing Techniques to Automotive Engineering University of Innsbruck
Orbital Multiferroicity in Pentalayer Rhombohedral Graphene MIT
Optimizing the Photodetector/Analog Front-End Interface in Optical Communication Receivers University of Toronto
Measurement-induced entanglement and teleportation on a noisy quantum processor Google Quantum AI, Google Research, Stanford University, University of Texas at Austin, Cornell University, University of Massachusetts, University of Connecticut, Auburn University, University of Technology Sydney, University of California, and Columbia University

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