Chip Industry Technical Paper Roundup: Mar. 3


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance 🔗 KAIST, Panmnesia, Peking University, Hanyang University, Pennsylvania State University Sputtering-driven formation of interstitial oxygen for intrinsic NIR detec... » read more

ReRAM-based Neo-Hebbian Synapses For Training Neuromorphic HW (IIT Madras, UCSB)


A new technical paper, "NeoHebbian synapses to accelerate online training of neuromorphic hardware," was published by researchers at IIT Madras and UC Santa Barbara. Abstract "Neuromorphic systems that employ advanced synaptic learning rules, such as the three-factor learning rule, require synaptic devices of increased complexity. Herein, a novel neoHebbian artificial synapse utilizing ReRA... » read more

Chip Industry Week in Review


Retaliations and countermoves leading up to planned trade talks between the U.S. and China led experts to wonder, 'Who's winning?' New activity on this front: China issued questionnaires to some U.S. semiconductor firms as part of an anti-dumping probe, demanding detailed data on sales, profit margins, logistics costs and Chinese customer names for analog chips. The probe appears aimed at ... » read more

Chip Industry Technical Paper Roundup: Mar. 25


New technical papers recently added to Semiconductor Engineering’s library: [table id=415 /] Find more semiconductor research papers here. » read more

Energy-Efficient Scalable Silicon Photonic Platform For AI Accelerator HW


A new technical paper titled "Large-Scale Integrated Photonic Device Platform for Energy-Efficient AI/ML Accelerators" was published by researchers at HP Labs, IIT Madras, Microsoft Research and University of Michigan. Abstract "The convergence of deep learning and Big Data has spurred significant interest in developing novel hardware that can run large artificial intelligence (AI) workload... » read more

Chip Industry Technical Paper Roundup: Mar. 5


New technical papers added to Semiconductor Engineering’s library this week. [table id=201 /] » read more

Chip Industry Technical Paper Roundup: Jan. 23


New technical papers added to Semiconductor Engineering’s library this week. [table id=189 /] More ReadingTechnical Paper Library home » read more

Chip Industry’s Technical Paper Roundup: October 31


New technical papers added to Semiconductor Engineering’s library this week. [table id=159 /] More Reading Technical Paper Library home » read more

Predicting Defect Properties In Semiconductors With Graph Neural Networks


A technical paper titled “Accelerating Defect Predictions in Semiconductors Using Graph Neural Networks” was published by researchers at Purdue University, Indian Institute of Technology (IIT) Madras, GE Research, and National Institute of Standards and Technology (NIST). Abstract: "Here, we develop a framework for the prediction and screening of native defects and functional impurities i... » read more

Chip Industry’s Technical Paper Roundup: October 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=150 /] Related Reading Technical Paper Library home » read more

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