Chip Industry’s Technical Paper Roundup: October 3

Next-gen AI accelerator design; LLM-assisted formal verification; neuromorphic HW for heterogeneous SoC; layered semimetals for heterogeneous electronics; friction between graphene and atomic force microscope tip; cryogenic IMC for quantum processors; modeling for EDA using ML; HW Trojan detection.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models Georgia Institute of Technology
From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches Princeton University
SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip Columbia University
Layered semimetal electrodes for future heterogeneous electronics IIT Madras and Indian Institute of Science Education and Research
Dynamically tuning friction at the graphene interface using the field effect University of Illinois Urbana-Champaign and University of California Irvine
Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs University of Stuttgart, Indian Institute of Technology Kanpur, University of California Berkeley, and Technical University of Munich
Improving Semiconductor Device Modeling for Electronic Design Automation by Machine Learning Techniques CSIRO, Peking University, National University of Singapore, and University of New South Wales
Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models National University of Singapore and Universitat Politecnica de Catalunya

Related Reading
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