Novel NorthPole Architecture Enables Low-Latency, High-Energy-Efficiency LLM inference (IBM Research)


A new technical paper titled "Breakthrough low-latency, high-energy-efficiency LLM inference performance using NorthPole" was published by researchers at IBM Research. At the IEEE High Performance Extreme Computing (HPEC) Virtual Conference in September 2024, new performance results for their AIU NorthPole AI inference accelerator chip were presented on a 3-billion-parameter Granite LLM. ... » read more

Using AI To Glue Disparate IC Ecosystem Data


AI holds the potential to change how companies interact throughout the global semiconductor ecosystem, gluing together different data types and processes that can be shared between companies that in the past had little or no direct connections. Chipmakers always have used abstraction layers to see the bigger picture of how the various components of a chip go together, allowing them to pinpoi... » read more

Verification Tools Straining To Keep Up


Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing pressures. Verification is no longer just about ensuring that functionality is faithfully represented in an implementation. That alone is an insolvable task, but verification has taken on many new re... » read more

Verifying Hardware CWEs in RTL Designs Generated by GenAI


A new technical paper titled "All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification" was published by researchers at Infineon Technologies. Abstract "Modern hardware designs have grown increasingly efficient and complex. However, they are often susceptible to Common Weakness Enumerations (CWEs). This paper is focused on the formal verification of CWEs in a dataset... » read more