Inferencing Efficiency

By Ed Sperling - 11 Jul, 2019 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks with Semiconductor Engineering about how to measure efficiency in inferencing chips, how to achieve the most throughput for the lowest cost, and what the benchmarks really show. » read more

Rethinking What Goes On A Chip

By Ed Sperling - 27 Jun, 2019 - Comments: 0

There are hints across the chip industry that chipmakers are beginning to reexamine one of the basic concepts of chip design. For more than 50 years, progress in semiconductors was measured by the ability to double the density of transistors on a piece of silicon. While that approach continues to be useful, the power and performance benefits have been dwindling for the past couple of nodes. ... » read more

CEO Outlook: Rising Costs, Chiplets, And A Trade War

By Ed Sperling - 26 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

Building An Efficient Inferencing Engine In A Car

By Ed Sperling - 05 Jun, 2019 - Comments: 0

David Fritz, who heads corporate strategic alliances at Mentor, a Siemens Business, talks about how to speed up inferencing by taking the input from sensors and quickly classifying the output, but also doing that with low power. » read more

CEO Outlook: It Gets Much Harder From Here

By Ed Sperling - 03 Jun, 2019 - Comments: 0

Controlling Variability And Cost At 3nm And Beyond

By Ed Sperling - 22 May, 2019 - Comments: 1

Richard Gottscho, executive vice president and CTO of Lam Research, sat down with Semiconductor Engineering to talk about how to utilize more data from sensors in manufacturing equipment, the migration to new process nodes, and advancements in ALE and materials that could have a big impact on controlling costs. What follows are excerpts of that conversation. SE: As more sensors are added int... » read more

From AI Algorithm To Implementation

By Brian Bailey - 10 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Spreading Intelligence From The Cloud To The Edge

By Kevin Fogarty and Ed Sperling - 04 Apr, 2019 - Comments: 0

The challenge of partitioning processing between the edge and the cloud is beginning to come into focus as chipmakers and systems companies wrestle with a massive and rapidly growing volume of data. There are widely different assessments of how much data this ultimately will include, but everyone agrees it is a very large number. Petabytes are simply rounding errors in this equation, and tha... » read more

Designing An AI SoC

By Ed Sperling - 11 Mar, 2019 - Comments: 0

Susheel Tadikonda, vice president of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures. https://youtu.be/fm0kxnj3DuM » read more

The Other Side Of Makimoto’s Wave

By Ann Mutschler - 06 Mar, 2019 - Comments: 0

Custom hardware is undergoing a huge resurgence across a variety of new applications, pushing the semiconductor industry to the other side of Makimoto's Wave. Tsugio Makimoto, the technologist who identified the chip industry’s 10-year cyclical swings between standardization and customization, predicted there always will be room in ASICs for general-purpose processors. But it's becoming mo... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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