Potentials And Issues Of Designing Fault-Tolerant Hardware Acceleration For Edge-Computing Devices

A technical paper titled “Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes” was published by researchers at University of Rome. Abstract: "High-performance embedded systems with powerful processors, specialized hardware accelerators, and advanced software techniques are all key technologies driving the growth of the IoT. By combining hardware and software tec... » read more

FPGA-Proven RISC-V System With Hardware Accelerated Task Scheduling

A technical paper titled “Enabling HW-based Task Scheduling in Large Multicore Architectures” was published by researchers at Barcelona Supercomputing Center, University of Campinas, University of Sao Paulo, and Arteris Inc. Abstract: "Dynamic Task Scheduling is an enticing programming model aiming to ease the development of parallel programs with intrinsically irregular or data-dependent... » read more

A Chiplet-Based FHE Accelerator Design Enabling Scalability And Higher Throughput

A technical paper titled “REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption” was published by researchers at Graz University of Technology and Samsung Advanced Institute of Technology. Abstract: "Fully Homomorphic Encryption (FHE) has emerged as a promising technology for processing encrypted data without the need for decryption. Despite its potential, its... » read more

Advantages, Disadvantages, And Use Cases Of FPGAs

A technical paper titled “Data Processing with FPGAs on Modern Architectures” was published by researchers at ETH Zürich. Abstract: "Trends in hardware, the prevalence of the cloud, and the rise of highly demanding applications have ushered an era of specialization that is quickly changing the way data is processed at scale. These changes are likely to continue and accelerate in the next... » read more

Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU (Ecole Polytechnique Montreal, IBM, Mila, CMC)

A new technical paper titled "BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU" was written by researchers at Ecole Polytechnique Montreal, IBM, Mila and CMC Microsystems. It was accepted for publication in the 2023, 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023) in Japan. Abstract: "We present a DNN accelerator that allows inference at arbitr... » read more

Kria KR260 Robotics Starter Kit: Unleashing Roboticists Through Hardware Acceleration

The Kria™ KR260 Robotics Starter Kit is a Kria SOM-based development platform for robotics and factory automation applications. It enables roboticists and industrial developers without FPGA expertise to develop hardware accelerated applications for robotics, machine vision, industrial communications and control. Developers benefit with greater flexibility from native ROS 2 (Humble Hawksb... » read more

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference

Abstract—"The growing prevalence and computational demands of Artificial Intelligence (AI) workloads has led to widespread use of hardware accelerators in their execution. Scaling the performance of AI accelerators across generations is pivotal to their success in commercial deployments. The intrinsic error-resilient nature of AI workloads present a unique opportunity for performance/energy i... » read more

AI Training Chips

Kurt Shuler, vice president of marketing at Arteris IP, talks with Semiconductor Engineering about how to architect an AI training chip, how different processing elements are used to accelerate training algorithms, and how to achieve improved performance. https://youtu.be/4cnBCX-9jlk     See other tech talk videos here. » read more

Tech Talk: eFPGA Acceleration

Achronix's Kent Orthner talks about when and why to use embedded FPGAs, and how they co-exist with—and compare to—other processing elements. [youtube vid=TXeIOmo7O9o] » read more

Emulation for Power

Solving power problems in today’s leading-edge SoCs requires not only the best architectural choices but advanced tools and techniques to determine the right path to take. This equates to a combination of hardware emulation and power analysis/optimization software tools. Design teams today must have real-life scenarios to accurately predict the power impact of their architectural decisions... » read more

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