HW Security: A Hybrid Verification Method Combining Simulation And Formal Verification (RPTU, UCSD)


A new technical paper titled "FastPath: A Hybrid Approach for Efficient Hardware Security Verification" was published by researchers at RPTU Kaiserslautern-Landau and UC San Diego. "We propose FastPath, a hybrid verification methodology that combines the efficiency of simulation with the exhaustive nature of formal verification. FastPath employs a structural analysis framework to automate th... » read more

Building A Robust Hardware Security Program


Even mature chip development teams and processes aren’t immune to security errors. While many semiconductor and hardware manufacturing organizations have mature development processes, existing security testing practices, and formal signoff requirements, the complexity and duration of the chip lifecycle creates many opportunities for security issues to be overlooked. Semiconductors now play... » read more