HDL Simulation Acceleration Solution For Microchip FPGA Designs

By Aldec - 23 Nov, 2020 - Comments: 0

Mission-critical FPGA designs for space and radar applications continue to increase in complexity, such that they require a comprehensive and robust verification environment. There are hardware-in-the-loop solutions in the market that utilize FPGA boards, but when it comes to establishing functional coverage and debugging the custom logic, users would typically need to go back to HDL simulation... » read more

Accelerate SoC Simulation Time of Newer Generation FPGAs

By Aldec - 26 Sep, 2018 - Comments: 0

Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. Read more. » read more

Debug Becomes A Bigger Problem

By Brian Bailey - 11 Feb, 2016 - Comments: 3

The EDA industry has invested enormous amounts of time and energy on the verification process, including new languages, new tools, new class libraries, new methodologies. But the one part of the cycle that defines that type of automation is debug. Development teams are spending half of their time in the debug process and the problem is growing. Part of the reason is that design and debug are... » read more

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tag: HDL simulator

HDL Simulation Acceleration Solution For Microchip FPGA Designs

Accelerate SoC Simulation Time of Newer Generation FPGAs

Debug Becomes A Bigger Problem