tag: heterogeneous computing

An Energy Efficient, Linux-Capable RISC-V Host Platform Designed For The Seamless Plug-In And Control Of Domain-Specific Accelerators
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Power and cost constraints in the internet-of-things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous arc... » read more

Heterogenous Computing & Cache Attacks
By Technical Paper Link - 12 Aug, 2022 - Comments: 0

Researchers at imec-COSIC, KU Leuven presented this paper titled "Double Trouble: Combined Heterogeneous Attacks on Non-Inclusive Cache Hierarchies" at the USENIX Security Symposium in Boston in August 2022. Note, this is a prepublication paper. Abstract: "As the performance of general-purpose processors faces diminishing improvements, computing systems are increasingly equipped with domai... » read more

Audio, Visual Advances Intensify IC Design Tradeoffs
By Ann Mutschler - 13 Jun, 2022 - Comments: 0

A spike in the number of audio and visual sensors is greatly increasing design complexity in chips and systems, forcing engineers to make tradeoffs that can affect performance, power, and cost. Collectively, these sensors generate so much data that designers must consider where to process different data, how to prioritize it, and how to optimize it for specific applications. The tradeoffs in... » read more

Dynamically Reconfiguring Logic
By Ed Sperling - 12 Jul, 2021 - Comments: 0

Dynamic reconfiguration of semiconductor logic has been possible for years, but it never caught on commercially. Cheng Wang, co-founder and senior vice president of software and engineering at Flex Logix, explains why this capability has been so difficult to utilize, what’s changed, how a soft logic layer can be used to control when to read, compute, steer, and write data back to memory, and ... » read more

ACAP At The Edge With The Versal AI Edge Series
By Xilinx - 30 Jun, 2021 - Comments: 0

This white paper introduces the AI Edge series to the Versal ACAP portfolio, a domain-specific architecture (DSA) that meets the strenuous demands of systems implemented in the 7nm silicon process. This series is optimized to meet the performance-per-watt requirements of edge nodes at or near the analog-digital boundary. Here, immediate response to the physical world is highly valued, and in ma... » read more

PCIe 5.0 Drill-Down
By Ed Sperling - 01 Apr, 2020 - Comments: 0

Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

Finding And Avoiding Concurrency Bugs
By Luis Murillo - 25 Apr, 2019 - Comments: 0

Understanding the intended and unintended interactions between hardware and software components is changing as architectures become more heterogeneous and interconnect topologies get more complicated. This affects performance, power consumption and cost of the project. Lots of universities are researching this from a software perspective, while a small number are looking at the implications fro... » read more

Benchmarks For The Edge
By Ed Sperling - 07 Feb, 2019 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about benchmarking in edge devices, particularly for convolutional neural networks. https://youtu.be/-beVEpKAM4M » read more

More 2.5D/3D, Fan-Out Packages Ahead
By Mark LaPedus - 15 Jan, 2019 - Comments: 0

A new wave of 2.5D/3D, fan-out and other advanced IC packages is expected to flood the market over the next year. The new packages are targeted to address many of the same and challenging applications in the market, such as multi-die integration, memory bandwidth issues and even chip scaling. But the new, advanced IC packages face some technical challenges. And cost remains an issue as advan... » read more

Formal Signoff
By Ed Sperling - 04 Dec, 2018 - Comments: 0

Xiaolin Chen, senior AE at Synopsys, looks at what’s good enough coverage, what makes one assertion better than another, and where the potential holes are in verification. https://youtu.be/nBtKE0gDHBU » read more

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