Unsolved Issues In Next-Gen Photomasks

By Mark LaPedus - 17 Feb, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

CEO Outlook: It Gets Much Harder From Here

By Ed Sperling - 03 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

1xnm DRAM Challenges

By Mark LaPedus - 18 Feb, 2016 - Comments: 3

At a recent event, Samsung presented a paper that described how the company plans to extend today’s planar DRAMs down to 20nm and beyond. This is an amazing feat. Until very recently, most engineers believed DRAMs would stop scaling at 20nm or so. Instead, Samsung is ramping up the world’s most advanced DRAMs—a line of 20nm parts—with plans to go even further. Micron and SK Hynix soo... » read more

Inside Inspection And Metrology

By Mark LaPedus - 18 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about inspection, metrology and other issues with Mehdi Vaez-Iravani, vice president of advanced imaging technologies at Applied Materials. What follows are excerpts of that conversation. SE: Today, the industry is working on a new range of complex architectures, such as 3D NAND and finFETs. For these technologies, the industry is clearly struggling... » read more

ALD Market Heats Up

By Mark LaPedus - 17 Sep, 2015 - Comments: 1

Amid the shift to 3D NAND, finFETs and other device architectures, the atomic layer deposition (ALD) market is heating up on several fronts. Applied Materials, for example, recently moved to shakeup the landscape by rolling out a new, high-throughput ALD tool. Generally, [getkc id="250" kc_name="ALD"] is a process that deposits materials layer-by-layer at the atomic level, enabling thin and ... » read more

Dealing With Atoms

By Mark LaPedus - 13 Jul, 2015 - Comments: 0

Chipmakers are ramping up a new range of device architectures, such as 3D NAND and finFETs. But to enable current and future devices, IC vendors will require new breakthroughs, including tools that can process tiny structures and films, even at the atomic level. The problem? There are gaps in terms of techniques that can process chips at the atomic level. Looking to help fill part of the ... » read more

Searching For Rare Earths Again

By Mark LaPedus - 19 Feb, 2015 - Comments: 0

Rare earths are back in the spotlight again. Rare earths are chemical elements found in the Earth’s crust. They are used in cars, consumer electronics, computers, communications, clean energy and defense systems. The big market for rare earths is magnets. In semiconductor production, rare earths are used in high-k dielectrics, CMP slurries and other applications. Last year, the World Tr... » read more

Will Materials Derail Moore’s Law?

By Mark LaPedus - 13 Nov, 2014 - Comments: 0

Is Moore’s Law slowing down? Clearly, chipmakers are struggling to keep up with Moore’s Law these days. But one sometimes forgotten and critical technology could easily derail Moore’s Law--materials. In fact, the cost and complexity for electronic materials are increasing at each node. “Chemical and gas commodity procurement spends are growing rapidly due to process complexity and un... » read more

Executive Viewpoint: Qualcomm On Process Technology

By Mark LaPedus - 23 Jan, 2014 - Comments: 3

Semiconductor Engineering sat down to discuss current and future process technology challenges with Geoffrey Yeap, vice president of technology at Qualcomm. SE: You have pointed out there is a fundamental shift taking place at the 28nm logic node. This is the first node in which mobile chips have been ramped up first within the foundries, ahead of computing-based ICs. Many believe that 28nm ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?