What Are FeFETs?

By Mark LaPedus - 16 Feb, 2017 - Comments: 1

The memory market is going in several different directions at once. On one front, the traditional memory types, such DRAM and flash, remain the workhorse technologies in systems despite undergoing some changes in the business. Then, several vendors are readying the next-generation memory types in the market. As part of an ongoing series, Semiconductor Engineering will explore where the new a... » read more

Measuring Atoms And Beyond

By Mark LaPedus - 21 Nov, 2016 - Comments: 0

David Seiler, chief of the Engineering Physics Division within the Physical Measurement Laboratory at the National Institute of Standards and Technology (NIST), sat down with Semiconductor Engineering to discuss the current and future directions of metrology. NIST, a physical science laboratory, is part of the U.S. Department of Commerce. What follows are excerpts of that conversation. SE: W... » read more

10nm Versus 7nm

By Mark LaPedus - 25 Apr, 2016 - Comments: 20

The silicon foundry business is heating up, as vendors continue to ramp their 16nm/14nm finFET processes. At the same time, they are racing each other to ship the next technologies on the roadmap—10nm and 7nm. But the landscape is complicated, with each vendor taking a different strategy. [getentity id="22865" e_name="Samsung"], for one, plans to ship its 10nm [getkc id="185" kc_name="fi... » read more

More Cores, Different Approaches

By Ed Sperling - 27 Aug, 2009 - Comments: 0

By Ed Sperling The general consensus among software developers is that some applications will never be able to take advantage of multiple cores, but that certainly doesn’t mean system designers can’t figure out ways to use more cores. Nor does it mean that all cores are created equal. The picture that is emerging from multiple chipmakers shows the following trends: More cores have lim... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

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by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

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AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

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tag: high k/metal gate

What Are FeFETs?

Measuring Atoms And Beyond

10nm Versus 7nm

More Cores, Different Approaches