Experts At The Table: Who Pays For Low Power?


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director o... » read more

Bit Mapping


The rule of thumb for semiconductor manufacturing is that big breakthroughs tend to last a decade, or about five process nodes. While the transistor already has spanned more than five decades and the IC more than four decades, the technology used to create them typically only lasts about one. 193nm lithography has been around more than a decade. Bets were being made publicly back at 45nm—o... » read more

New Issues In Signoff


By Ed Sperling Signoff has always been a challenge at every stage of an SoC design flow. No matter how good a design looks, or how well a prototype works, there are still problems that can crop up at any stage of the design flow all the way into manufacturing that can leave engineering teams shaking their heads. Even at mainstream process nodes, respins are common. At advanced nodes—part... » read more

New Challenges, New Name


As you’ll notice today, we’ve changed our name from Low Power Engineering to Low-Power/High-Performance Engineering. We don’t take name changes lightly—we've been discussing this in depth with readers, sponsors, and researchers for the past six months. The almost universal conclusion is there is a big shift underway in the semiconductor industry today, and our new logo is a better refle... » read more

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