Bit Mapping

Changes on the manufacturing side will have a bigger impact on low-power, high-performance designs in the future.


The rule of thumb for semiconductor manufacturing is that big breakthroughs tend to last a decade, or about five process nodes. While the transistor already has spanned more than five decades and the IC more than four decades, the technology used to create them typically only lasts about one.

193nm lithography has been around more than a decade. Bets were being made publicly back at 45nm—one node after EUV originally was supposed to become commercially viable—that even immersion wouldn’t last beyond 22nm. Billions of dollars later, with more billions being sunk into getting the EUV power source up to speed, it still isn’t ready. It may never be, which is why we’re now facing double patterning issues at 20nm, and potentially triple and quadruple patterning at 14nm.

While technically this multi-patterning approach will work, it’s not very efficient to have to pattern masks three and four times. It’s not even cost-effective, and it may have an adverse impact on both performance and power. Masks essentially create seams when they’re overlaid on top of one another, and the best way to account for those seams is either through very restrictive design rules—something that makes design teams wonder why you’re moving to the next process node in the first place—or margin. At 28nm, margin was shown to affect performance and power budgets. At each new node, that effect is magnified.

One alternative to emerge is fully depleted SOI (FD-SOI), which at 28nm has provided many of the same benefits of finFETs in controlling leakage and boosting performance. ST Microelectronics is the poster child for this technology—a variant known as ultra-thin body and box—which it rolled out last year using body biasing to dynamically swap off performance and power. At 28nm, this can still be done with immersion. At the next process node, if EUV isn’t ready, ST will require double patterning, as well.

A second alternative is to improve the technology at 28nm and not move to the next node. Foundries are considering adding finFETs at 28nm to control leakage, possibly in conjunction with FD-SOI, which will provide many of the power/performance improvements of moving to the next nodes without the double patterning problem. More fins can be added to the finFET transistors to extend this approach, as well.

A third approach is stacking the die, which is particularly favored by analog IP vendors and makers of high-performance computer chips. On the IP side, it lengthens their return on investment. On the computer side, it improves performance by widening signal channels and shortening wire lengths. Many are convinced this approach will become mainstream at some point, either with 2.5D packaging or full 3D-IC approaches.

A fourth approach is to change the manufacturing process altogether. This has always been the choice of last resort because it threatens business models across the supply chain—a well-oiled machine that has overseen a steady drop in cost per transistors since the introduction of Moore’s Law. Directed self-assembly can be done using relatively inexpensive equipment. Carbon nanotubes can be grown for CNT finFETs and wrapped with a conformal gate. So far, no one knows at what speed, what cost, and with what consistency. But it’s clear they are seriously looking at alternatives right now.

No matter which path is taken—or paths—it’s clear that change is afoot. EUV’s future already is limited. The clock has been ticking since 65nm. There’s no such thing as EUV immersion. And there are enough options at various stages of development that something will likely pan out.

While all of this appears to be one step removed from the SoC design world, it still will have a significant impact on future designs. All of these efforts have a big impact on controlling leakage and improving performance, which translates into longer battery life and higher clock frequencies. These changes also could eliminate some of the physical effects headaches designers now contend with, such as electromigration and electromagnetic interference. Design and manufacturing have always been two very separate worlds with different concerns and languages, but increasingly they are becoming bit-mapped representations of each other—even if it is hard to discern that through the multiple mask layers.

—Ed Sperling