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Domain-Specific Memory


Domain-specific computing may be all the rage, but it is avoiding the real problem. The bigger concern is the memories that throttle processor performance, consume more power, and take up the most chip area. Memories need to break free from the rigid structures preferred by existing software. When algorithms and memory are designed together, improvements in performance are significant and pr... » read more

Usage Models Driving Data Center Architecture Changes


Data center architectures are undergoing a significant change, fueled by more data and much greater usage from remote locations. Part of this shift involves the need to move some processing closer to the various memory hierarchies, from SRAM to DRAM to storage. There is more data to process, and it takes less energy and time to process that data in place. But workloads also are being distrib... » read more

Hidden Costs In Faster, Low-Power AI Systems


Chipmakers are building orders of magnitude better performance and energy efficiency into smart devices, but to achieve those goals they also are making tradeoffs that will have far-reaching, long-lasting, and in some cases unknown impacts. Much of this activity is a direct result of pushing intelligence out to the edge, where it is needed to process, sort, and manage massive increases in da... » read more

Priorities Shift In IC Design


The rush to the edge and new applications around AI are causing a shift in design strategies toward the highest performance per watt, rather than the highest performance or lowest power. This may sound like hair-splitting, but it has set a scramble in motion around how to process more data more quickly without just relying on faster processors and accelerators. Several factors are driving th... » read more

Speeding Up 3D Design


2.5D and 3D designs have garnered a lot of attention recently, but when should these solutions be considered and what are the dangers associated with them? Each new packaging option trades off one set of constraints and problems for a different set, and in some cases the gains may not be worth it. For other applications, they have no choice. The tooling in place today makes it possible to de... » read more

Foveated Rendering


Virtual Reality (VR) is becoming increasingly popular due to its ability to immerse the user into an experience. Those experiences can vary from watching a movie in a simulated theatre, having a look at your personal pictures as though they were paintings in a museum or finding yourself in front row seats of a huge sporting event. These specific experiences don’t stress the device hardware to... » read more

More Performance At The Edge


Shrinking features has been a relatively inexpensive way to improve performance and, at least for the past few decades, to lower power. While device scaling will continue all the way to 3nm and maybe even further, it will happen at a slower pace. Alongside of that scaling, though, there are different approaches on tap to ratchet up performance even with chips developed at older nodes. This i... » read more

Customizing Power And Performance


Designing chips is getting more difficult, and not just for the obvious technical reasons. The bigger issue revolves around what these chips going to be used for-and how will they be used, both by the end user and in the context of other electronics. This was a pretty simple decision when hardware was developed somewhat independently of software, such as in the PC era. Technology generally d... » read more

Automated Body Bias Validation For High Performance, Low Power Electronics


Using a device’s body bias effect allows designers to tune a circuit’s behavior to meet both power and performance specifications, but getting it right isn’t always easy. Accurate, fast, automated body bias verification is critical to ensure today’s complex designs meet demanding performance, reliability, and power usage specifications. To read more, click here. » read more

Low Power Trends Toward FinFET


My previous blog, Power Reduction Techniques, covered which low power techniques were applicable for various process nodes, from larger planar CMOS process technologies through finFET. The 16 and 14nm finFET-based process nodes are moving into production this year, and we are seeing many companies rapidly move their designs to finFET. In my last post, I noted some of the reasons why finFET is s... » read more

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