tag: high performance

Chiplet Interconnects Add Power And Signal Integrity Issues
By Adam Kovac - 12 Dec, 2024 - Comments: 0

The flexibility and scalability offered by chiplets make them an increasingly attractive choice over planar SoCs, but the rollout of increasingly heterogeneous assemblies adds a variety of new challenges around the processing and movement of data. Nearly all of the chiplets in use today were designed in-house by large systems companies and IDMs. Going forward, third-party chiplets will begin... » read more

Tools Needed To Track, Catalog Hardware Vulnerabilities
By Adam Kovac - 05 Dec, 2024 - Comments: 0

Monitoring for cyberattacks is a key component of hardware-based security, but what happens afterward is equally important. Logging and cataloging identified hardware vulnerabilities to ensure they are not repeated is essential for security. In fact, thousands of weak points have been identified as part of the chip design process, and even posted publicly online. Nevertheless, many companies... » read more

MCU Changes At The Edge
By Ed Sperling - 03 Jun, 2024 - Comments: 0

Microcontrollers are becoming a key platform for processing machine learning at the edge due to two significant changes. First, they now can include multiple cores, including some for high performance and others for low power, as well as other specialized processing elements such as neural network accelerators. Second, machine learning algorithms have been pruned to the point where inferencing ... » read more

Aeonic Generate GGM High Performance SoC Clock Generation Module
By Movellus - 24 Apr, 2024 - Comments: 0

Core counts have been increasing steadily since IBM's debut of the Power 4 in 2001, eclipsing 100 CPU cores and over 1,000 for AI accelerators. While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always going to be symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialize... » read more

PLANAR: A Programmable Accelerator For Near-Memory Data Rearrangement
By Arm - 12 Oct, 2022 - Comments: 0

Many applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques rearrange sparse data into a dense representation, improving locality and cache utilization. However, prior proposals in this space fail to provide a design that (i) scales with m... » read more

Simplifying AI Edge Deployment
By Ed Sperling - 10 Oct, 2022 - Comments: 0

Barrie Mullins, vice president of product at Flex Logix, explains how a programmable accelerator chip can simplify semiconductor design at the edge, where chips need to be high performance as well as low power, yet developing everything from scratch is too expensive and time-consuming. Programmability allows these systems to stay current with changes in algorithms, which can affect everything f... » read more

Deep Reinforcement Learning to Dynamically Configure NoC Resources
By Technical Paper Link - 17 Jun, 2022 - Comments: 0

New research paper titled "Deep Reinforcement Learning Enabled Self-Configurable Networks-on-Chip for High-Performance and Energy-Efficient Computing Systems" from Md Farhadur Reza at Eastern Illinois University. Find the open access technical paper here. Published June 2022. M. F. Reza, "Deep Reinforcement Learning Enabled Self-Configurable Networks-on-Chip for High-Performance and Energ... » read more

Speeding Up AI Algorithms
By Ed Sperling - 18 Apr, 2022 - Comments: 0

AI at the edge is very different than AI in the cloud. Salvador Alvarez, solution architect director at Flex Logix, talks about why a specialized inferencing chip with built-in programmability is more efficient and scalable than a general-purpose processor, why high-performance models are essential for getting accurate real-time results, and how low power and ambient temperatures can affect the... » read more

Designing High-Performance Electronics For Today’s Hyperconnected Systems
By Cadence - 08 Sep, 2021 - Comments: 0

With the rapid evolution of hyperconnected devices that are managing constant and near-instantaneous data from anywhere and at any time, designing at each new technology node must overcome design and integration complexity. To do so requires automated solutions to process the scale of modern designs. Cadence system analysis solutions operate on unimaginably huge amounts of data, scaling algorit... » read more

Domain-Specific Memory
By Brian Bailey - 11 Mar, 2021 - Comments: 2

Domain-specific computing may be all the rage, but it is avoiding the real problem. The bigger concern is the memories that throttle processor performance, consume more power, and take up the most chip area. Memories need to break free from the rigid structures preferred by existing software. When algorithms and memory are designed together, improvements in performance are significant and pr... » read more

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