tag: HLS

ESL Flow is Dead
By Brian Bailey - 28 Apr, 2016 - Comments: 3

It was 20 years ago that Gary Smith coined the term [getkc id="48" comment="Electronic System Level"] (ESL). He foresaw the next logical migration in abstraction up from the [getkc id="49" comment="Register Transfer Level"] (RTL) to something that would be capable of describing and building complex electronic systems. He also saw that the future of EDA depended upon who would control that marke... » read more

ESL: 20 Years Old, 10 To Go
By Brian Bailey - 23 Sep, 2015 - Comments: 2

It is a common perception that the rate of technology adoption accelerates. In 1873, the telephone was invented and, after 46 years, it had been adopted by one-quarter of the U.S. population. Television, invented in 1926 took 26 years. The PC in 1975 took just 16 years. It took only 7 years after the introduction of the Internet in 1991 before it was seeing significant levels of adoption. So... » read more

Blog Review: July 22
By Jesse Allen - 22 Jul, 2015 - Comments: 0

It's been a hot summer for high-level synthesis, says Cadence's Dave Pursley in a collection of the season's HLS highlights spanning DAC to SystemC Japan. Mentor's Harry Foster continues his survey of functional verification with a look at the adoption trends of various verification technologies, and the reasons one-third of projects use emulation or FPGA prototyping. Synopsys' Navraj Nan... » read more

Does Fast Simulation Help Debug Productivity?
By Brian Bailey - 09 Apr, 2015 - Comments: 0

It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by [getentity id="22032" e_name="Cadence"] at the recent Design and Verification Conference (DVCon) in Santa Clara, CA. Brian Bailey, technology editor for Semiconductor Engineer was the moderator for the panel and broke the news to the crowd. Cadence had developed a logic [getkc id... » read more

RTL Power Reduction And High Level Synthesis Report 2013
By Calypto - 09 Jul, 2014 - Comments: 0

This report covers trends in the area of low-power design and C-based design. The report analyzes the survey results of 648 engineers and engineering managers and identifies relevant emerging trends. To view this white paper, click here. » read more

Blog Review: June 25
By Ed Sperling - 25 Jun, 2014 - Comments: 0

Is the Amazon Fire smart phone a paradigm shift? Cadence’s Brian Fuller looks at the first application-specific smart phone and why it’s noteworthy—regardless of how well it fares against phones made by Apple and Samsung. Rambus’ Deepak Chandra Sekar digs deep into interconnect technology and where the prevailing winds are blowing—copper barrier/cap/liner optimization, a slowdown i... » read more

High Level Synthesis: Significant Differences Remain
By Brian Bailey - 09 Apr, 2014 - Comments: 1

In part 1 of this experts series on high-level synthesis (HLS), Semiconductor Engineering sat down with Mike Meredith, vice president of technical marketing at Cadence/Forte Design Systems; Mark Warren, Solutions Group director at Cadence; Thomas Bollaert, vice president of application engineering at Calypto; and Devadas Varma, senior director at Xilinx. The initial part of the discussion looke... » read more

Will History Repeat Itself?
By Brian Bailey - 24 Oct, 2013 - Comments: 0

Hands up — how many people read the books by Clayton Christensen, books such as The Innovator’s Dilemma? His books were talked about endlessly in the corridors of the EDA companies when they first came out. They all wanted to identify the next disruption and could find reasons why almost every new tool was going to be disruptive. For people not familiar with his work, his main premise wa... » read more

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