Week In Review: Design, Low Power

By Jesse Allen - 29 Oct, 2021 - Comments: 0

Arteris IP uncorked its initial public offering this week, a rare occurrence for a semiconductor IP vendor over the past couple decades. The stock began trading on the Nasdaq Global Market on Wednesday under the ticker symbol AIP, gaining more than 40% on its first day. Tools Codasip updated its Studio processor design toolset. Version 9.1 includes an expanded bus support with full AXI for ... » read more

Blog Review: April 21

By Jesse Allen - 21 Apr, 2021 - Comments: 0

Synopsys' Taylor Armerding warns that without making cybersecurity a priority, companies may be positioning themselves as the weak link in the supply chain, and provides some tips for protecting both the company and its customers. Siemens EDA's Simon Favre points to critical area analysis and design for manufacturing as two important strategies to improve IC yield and quality. Cadence's P... » read more

Manufacturing Bits: Jan. 30

By Mark LaPedus - 30 Jan, 2018 - Comments: 0

SRC’s new R&D centers The Semiconductor Research Corp. has launched a network of research centers within its recently-announced Joint University Microelectronics Program (JUMP). SRC officially launched the 5-year, $200 million program on Jan. 1. With various research centers, the mission of JUMP is to lay the groundwork that extends the viability of Moore’s Law through 2040. The idea is... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Honeywell Aerospace

Week In Review: Design, Low Power

Blog Review: April 21

Manufacturing Bits: Jan. 30