中文 English

Week In Review: Design, Low Power

Arteris IPO; tools for TSMC 3DFabric; ultra-low energy DSP; Wi-Fi, radar acquisitions.

popularity

Arteris IP uncorked its initial public offering this week, a rare occurrence for a semiconductor IP vendor over the past couple decades. The stock began trading on the Nasdaq Global Market on Wednesday under the ticker symbol AIP, gaining more than 40% on its first day.

Tools
Codasip updated its Studio processor design toolset. Version 9.1 includes an expanded bus support with full AXI for high-performance designs, as well as improved support for LLVM and improved code density. It also adds support for ISA sub-targets that reduce the maintenance of different SDKs for different ISA configurations.

Ansys worked with TSMC to simulate the temperature of 3D and 2.5D electronic systems containing multiple chips stacked closely together using TSMC 3DFabric 3D silicon stacking and advanced packaging technologies. The simulation solution is based on Ansys’ Icepak.  The companies also developed a high-capacity hierarchical thermal solution, using Ansys RedHawk-SC Electrothermal, to analyze complete chip-and-package systems with high-fidelity results.

Cadence’s Integrity 3D-IC platform for 3D-IC planning, implementation and system analysis has been enabled for TSMC’s 3DFabric technologies. Additionally, Cadence’s Tempus Timing Signoff Solution now supports a new stacking static timing analysis signoff methodology that aims to shorten design turnaround time.

Siemens Digital Industries Software’s Calibre nmPlatform for physical verification and Analog FastSPICE Platform have been certified for TSMC’s N3 and N4 processes. Certifications for the Aprisa place-and-route solution are in progress. Additionally, to support the TSMC 3DFabric technologies, the Xpedition Package Designer (xPD) tool was updated to support Integrated Fan-Out Wafer Level Packaging (InFO) design-rule handling with automated avoidance and correction. Calibre 3DSTACK, DRC, and LVS are also enabled and certified for TSMC 3DFabric technologies including InFO, CoWoS, and TSMC-SoIC. A Design for Testability (DFT) flow for TSMC’s 3D silicon stacking architecture is also available.

Cadence reported third quarter 2021 financial results. Revenue was $751 million, a 12.6% increase compared to the same period in 2020. “We exceeded our guidance on all key metrics for the third quarter and as a result, I am pleased to raise our outlook for the year,” said John Wall, senior vice president and CFO of Cadence. For 2021, the company expects total revenue in the range of $2.96 billion to $2.98 billion.

S2C uncorked its Logic Matrix LX2 FPGA prototyping platform. Built on the Xilinx Virtex UltraScale+ VU19P, LX2 targets verification of the hardware and software components of hyperscale designs ranging into the billions of ASIC gates. Holding up to 8 FPGAs in a single enclosure, the LX2 can be used stand-alone or deployed in a standard server rack with up to eight LX2s totaling 64 FPGAs.

IP
Cadence revealed the Tensilica HiFi 1 DSP, an ultra-low energy DSP that targets small, always-on and always-listening battery devices such as TWS earbuds, hearing aids, Bluetooth headsets, smart watches, and other wearables. It provides ultra-low energy encoding and playback of Low Complexity Communication Codec (LC3) and other Bluetooth codecs as well as keyword spotting for voice wake-up. Compared to the HiFi 3 DSP, it has 11% to 16% lower area, 60% to 73% greater cycle and energy efficiency for ML-based “OK Google” keyword spotting and person detect applications, and greater than 18% cycle efficiency and 14% energy efficiency for LC3 decoding.

Synopsys announced a portfolio of DesignWare Interface and Foundation IP on the TSMC N4P process will be available in Q1 2022. The portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems. IP prototyping and software development kits are also available.

FPGA
Xilinx announced a number of audio/video system and IP integrator companies are using Zynq UltraScale+ EV Multi-Processor (MP) SoC and Zynq-7000 SoC devices in broadcast and professional AV products. The solutions include video IP cores from Adeas and Nextera for ST 2110 AV-over-IP systems; Macnica Technology’s single-chip, full-stack ME10 SoC for the AIMS IPMX standard; Osprey Video’s Talon broadcast encoders and decoders; and XVTEC’s XVC-ULTRA broadcast encoder.

Xilinx reported second quarter 2022 financial results with revenues of $936 million, up 7% over the previous quarter. “We saw broad strength in the vast majority of our markets in the quarter, driven by record performance from the Industrial, Auto, Broadcast and Consumer end markets, as well as improvement in the Aerospace & Defense end market,” said Victor Peng, Xilinx president and CEO. “We also believe we remain on track for regulatory approval for the AMD transaction and to close by the end of the calendar year.”

Memory
JEDEC updated the DDR5 SDRAM standard, JESD79-5A. The update includes features designed to enhance reliability and performance in a wide range of applications involving client systems and high-performance servers, such as bounded fault error-correction support, Soft Post-Package Repair (sPPR) undo and lock, Memory Built-In Self-Test Post Package Repair (MBIST and mPPR), Adaptive RFM, and an MR4 extension. JESD79-5A also expands the timing definition and transfer speed of DDR5 up to 6400 MT/s for DRAM core timings and 5600 MT/s for IO AC timings to enable the industry to build an ecosystem up to 5600 MT/s.  The nomenclature for core timing parameters and their respective definitions has been revamped to closely align with the upcoming JEDEC JESD400-5 DDR5 Serial Presence Detect (SPD) Contents V1.0 standard.

Consumer & IoT
Renesas acquired Celeno Communications in an all-cash transaction valued at approximately $315 million based on milestones. Celeno provides wireless communications including advanced Wi-Fi chipsets and software solutions for high-performance home networks, smart buildings, enterprise, and industrial markets. It also offers high-resolution imaging technology that tracks and analyzes the motion, behavior, and location of people and objects using standard Wi-Fi.

Infineon announced EZ-PD BCR (Barrel Connector Replacement), a highly integrated USB-C controller, together with the USB-C connector, which replaces barrel connectors, custom connectors, or legacy USB connectors in electronic devices. It supports the USB Power Delivery standard that interoperates with all USB-C power adapters without the need of firmware development.

Automotive
Indie Semiconductor will acquire Analog Devices’ Symeo radar division. Symeo provides RF and sensor technologies for real-time position detection and distance measurement in high precision radar solutions, and Indie sees this as a way to accelerate its entry into the radar market. “Bringing Analog Devices’ Symeo radar division under the Indie umbrella significantly expands our sensor modality capabilities and affirms our commitment to the radar market,” said Donald McClymont, co-founder and CEO of Indie Semiconductor. Joining through the acquisition will be approximately 35 team members specializing in radar hardware and software development for emerging safety system applications; it will also include 120 granted and pending radar-related patents. Terms of the deal were not disclosed.

Infineon introduced a new automotive security controller. SLI37 acts as a trust anchor to secure safety-critical automotive applications like 5G-ready eUICC (eCall), V2X communication, car access, or SOTA updates.

Honeywell Aerospace is using Ansys’ model-based development solutions in development, analysis, and certification of safety-critical embedded systems in autonomous vehicles, electric aircraft, and safety-critical code across industry verticals.

Infineon added a new coreless automotive current sensor. XENSIV TLE4972 targets xEV applications like traction inverters used in hybrid and battery-driven vehicles, as well as for battery main switches. A differential sensing structure means neither core nor shield are required to protect the sensor against stray fields. The integrated EEPROM allows the sensor to be customized for different applications and supports measurement ranges up to 2 kA.

Sustainability
Imec launched its Sustainable Semiconductor Technologies and Systems (SSTS) research program, an effort to identify and quantify the ecological footprint of the semiconductor and IC industry. Apple joined as the first public partner in the program. “Companies realize they can only become carbon neutral if their whole supply chain follows suit. So, that is the snowball effect we want to create – together with Apple – today: I would like to call upon the whole semiconductor value chain not to stand at the side, but to act as one and to join forces with us to cut back the entire semiconductor industry’s ecological footprint,” said Luc Van den hove, CEO of Imec.

Awards
Renu Mehra, R&D group director for the Digital Design Group at Synopsys, was selected as the 2021 recipient of the Marie R. Pistilli Women in Electronic Design Award. The award announcement notes that Mehra is “responsible for many advanced technologies including RTL synthesis and optimization, clock gating, multi-voltage design and power management, as well as congestion, PPA and runtime optimizations. She is a pioneer in design automation for power management and provided one of the early visions for automated solutions in this area. As one of the founding members of the IEEE 1801 working group that created the Unified Power Format, she helped shape what is now the dominant power intent specification format for the semiconductor industry.”

 



Leave a Reply


(Note: This name will be displayed publicly)