June’19 Startup Funding

By Jeff Dorsch - 11 Jul, 2019 - Comments: 0

During the month of June, there were 15 startups that brought in funding rounds of $100 million or more, as investors continued to chase deals in cybersecurity, automotive technology, semiconductors, and a variety of services. There were no billion-dollar deals as spring slid into summer; yet, those 15 companies together raised a total of about $3.13 billion. Aurora Innovation, the developer... » read more

Week In Review: Design, Low Power

By Jesse Allen - 01 Mar, 2019 - Comments: 0

Tools & IP OneSpin Solutions debuted the Hardware Metric Calculation (HMC) App, which uses automatically extracted design information to calculate key hardware metrics to comply with functional safety standards. In particular, it focuses on automotive and autonomous driving SoCs needing to meet the highest functional safety requirements defined by the ISO 26262 standard. The HMC App calcul... » read more

The Week In Review: Design

By Jesse Allen - 06 Apr, 2018 - Comments: 0

Tools Mentor, a Siemens business, filled in the last of the hardware configurations for its Veloce Strato emulation family, creating a full upgrade path. Users can initially purchase only the hardware that they need (StratoTiL) and if later they require more capacity (StratoTi) or the ability to handle larger designs (StratoT), they can incrementally add the necessary hardware to their existin... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 30 Jun, 2017 - Comments: 0

Chipmakers Toshiba and its fab partner, Western Digital, have jointly rolled out a 96-layer 3D NAND product amid a legal dispute. The companies have developed prototype samples of a 96-layer 3D NAND device. Samples of the new 96-layer product, which is a 256 gigabit (32 gigabytes) device, is scheduled for release in the second half of 2017 and mass production is targeted for 2018. Separately, ... » read more

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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June’19 Startup Funding

Week In Review: Design, Low Power

The Week In Review: Design

The Week In Review: Manufacturing

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