Week In Review: Design, Low Power

Functional safety compliance; DSP for radar, lidar, 5G; secure environments for embedded.


Tools & IP
OneSpin Solutions debuted the Hardware Metric Calculation (HMC) App, which uses automatically extracted design information to calculate key hardware metrics to comply with functional safety standards. In particular, it focuses on automotive and autonomous driving SoCs needing to meet the highest functional safety requirements defined by the ISO 26262 standard. The HMC App calculates the key safety metrics set by ISO 26262, including single-point fault metric (SPFM) to reflect the robustness of the SoC with respect to safety goal violation by individual faults, as well as latent fault metric (LFM) to reflect the robustness of the SoC with respect to safety goal violation by multiple-point faults such as faults in safety mechanisms. The HMC App also calculates probabilistic metric of random hardware failures (PMHF) to measure the residual risk of the safety architecture.

Cadence added a new high-performance DSP to its ConnX family, the Tensilica ConnX B20 DSP, targeting automotive and 5G communications markets, including radar, lidar, and vehicle-to-everything (V2X). According to Cadence, the DSP’s enchanced ISA and clock-speed increase means it processes parts of the communication processing chain up to 30X faster and parts of the radar/lidar processing chain up to 10X faster compared to the ConnX BBE32EP DSP. The ConnX B20 DSP has a 512-bit vector width up to 128 MACs, can load 1024 bits of data each cycle and achieves 1.4GHz or greater frequency in 16nm process technology.

Synopsys launched an Enhanced Security Package for DesignWare ARC HS Processors to aid in development of secure, isolated environments in high-performance embedded applications. The package incorporates a range of features, including integrity protection, multiple privilege levels, and a watchdog timer to help protect SoCs against both logical and physical attacks. Additionally, randomization of the base address for software prevents return-oriented programming (ROP) and jump-oriented programming (JOP) in larger systems running Linux.

Aldec released a new embedded system development board, TySOM-3A-ZU19EG, focused on the development of AI, Deep-learning Neural Network (DNN) and other applications dependent on complex algorithm acceleration in firmware. It features a Xilinx Zynq UltraScale+ ZU19EG FFVB1517 MPSoC, which has more than 1 million logic cells, and a quad-core ARM Cortex-A53 platform running at up to 1.5GHz. The kit provides 64-bit processor scalability and combines real-time control with soft and hard engines for SoC prototyping solution, IP verification, graphics, video, packet processing and early software development.

Truechip launched a debug GUI, dubbed TruEYE. According to CEO Nitin Kishore, the tool “provides at a glance, in-depth and relevant information like FSM state, important configurations, the commands being carried on, the previous and next transactions, suggested reasoning for the error, thus enabling very fast debug of the root cause.”

Racyics extended its line of Adaptive Body Bias enabled IP, adding an Ultra-Low-Voltage fast lock-in ADPLL enabled for ABB and DVFS as well as a 10 MHz, 5µW Ultra-Low-Power ADFLL Clock generator with flexible reference input clock from 32kHz to 1 MHz.

Arasan Chip Systems uncorked MIPI D-PHY / C-PHY Combo IP supporting speeds of up to 2.5 Gbps for TSMC’s 22nm ULP process. The IP is integrated with the company’s CSI Tx, CSI Rx, DSI Tx and DSI Rx IP.

Palma Ceia’s LTE Cat NB1/NB2 RF transceiver IP has been integrated with Synopsys’ DesignWare ARC EM9D Processor IP to provide a complete low-power NB-IoT IP solution for both standalone or embedded modems. The ready-to-use NB-IoT solution conforms to the latest LTE Release 14 standard. Palma Ceia’s RF transceiver IP is fully characterized in 40nm processes.

Toshiba Memory Corporation utilized Cadence’s CMP Process Optimizer, a model calibration and prediction tool, in development of its advanced 3D flash memory devices. Toshiba cited 95.7% accuracy to silicon as a result of using the tool.

Minima Processor inked a Strategic IP Agreement with Arm, giving it access to Artisan Physical IP for 22nm ultra-low leakage (ULL) process technology. The agreement allows Minima to optimize Arm-based SoC designs featuring Minima Dynamic Margining IP ultra-low power technology.

Imagination Technology and Andes Technology teamed up to integrate the new N22 RISC-V MCU IP from Andes with Imagination’s Ensigma low-power IP for Wi-Fi, Bluetooth, IEEE 802.15.4 and GNSS to provide a fully integrated, off-the-shelf solution for IoT applications such as home automation and wearables. The N22 has a 2-stage pipeline and can reach over 750MHz at TSMC 28nm under worst case conditions.

Cadence’s Tensilica functional safety portfolio and its design processes achieved certification of ISO 26262 compliance up to ASIL D for the development of automotive applications by TÜV SÜD and SGS-TÜV Saar.

OneSpin’s 360 Quantify Tool Qualification Kit was certified by TÜV SÜD for the ISO 26262 (TCL3/ASIL D), IEC 61508 (T2/SIL 3) and EN 50128 (T2/SIL 3) functional safety standards. Quantify is designed to identify problems in the verification process itself, allowing previous tools to be classified as TCL1 so they do not require further qualification.

ANSYS reported Q4 2018 financial results with revenue of $415.4 million. On a GAAP basis, income per share was $1.79, while non-GAAP income was $2.13 per share. The company adopted new accounting standards this year; under the previous rules, Q4 2018 revenue was $335.9 million, up 11% from $302.3 million in the same quarter last year. GAAP income per share was $1.04, up 70% from $0.61 in Q4 2017, while non-GAAP income was $1.39 per share, up 30% from $1.07.

For the full 2018 year, ANSYS’ revenue was $1,293.6 million. GAAP income per share was $4.88, and non-GAAP income per share was $5.98. Under the previous accounting rules, full year revenue was $1,216.5 million, up 11% from $1,095.3 million in 2017. GAAP earnings per share stood at $4.15, up 39% from $2.98 last year, while non-GAAP earnings per share were $5.30, up 32% from $4.01. “I am confident we are tracking towards our 2020 objective of sustained, double-digit revenue growth at industry leading margins,” said President and CEO Ajei Gopal. CFO Maria Shields added, “To achieve both our near-term and longer-term growth objectives, we will move forward with investments in our core products, high-growth adjacent markets and our business infrastructure to continue building the platform to scale our business.” For the next year, the company expects revenue of $1.4 to $1.465 billion. The recent acquisitions of electromagnetic analysis company Helic and materials information company Granta were valued at approximately $261.5 million combined.

AI chip startup GreenWaves Technologies raised 7 million euro (about $7.96 million) in its Series A funding round. The round was co-led by Huami, with the participation of Soitec, its seed round lead investor, and other investors. GreenWaves makes ultra-low-power AI embedded processors for battery-operated edge devices. The funds will be used to ramp sales of its first product and complete the development of its second generation product.

Verification 3.0 Innovation Summit: Mar. 19, 1 p.m.-8 p.m., in Santa Clara, CA. A half-day seminar focused on advanced technical content around a range of topics on verification innovation, including a keynote by former Cadence CEO Joe Costello, three sessions, and a mini exhibit and reception. The event is free but registration is required.

DATE 2019: Mar. 25-29 in Florence, Italy. The conference and exhibition will feature keynotes on heterogeneous computing in cloud and HPC as well as the limitations of modeling frameworks for intelligent systems. Sessions will highlight emerging design technologies, design and test of secure systems, embedded systems for deep learning, and more. Advanced registration closes Mar. 13.

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