Memory Choices Grow

By Ed Sperling - 24 Nov, 2015 - Comments: 1

Memory is becoming one of the starting points for SoC architectures, evolving from a basic checklist item that was almost always in the shadow of improving processor performance or lowering the overall power budget. In conjunction with that shift, chipmakers must now grapple with many more front-end decisions about placement, memory type and access prioritization. There are plenty of rules ... » read more

Overcoming The Design Bottleneck

By Brian Bailey - 12 Nov, 2015 - Comments: 0

SoCs control most advanced electronics these days and functionality, quality, power and security are a combination of both hardware and software. All throughout the development of today's complex systems, the memory hierarchy has remained the same—preserving the notion of a continuous computing paradigm. Today, that decision is leading to performance and power issues. There are several rea... » read more

Is The 2.5D Supply Chain Ready?

By Ed Sperling - 28 Sep, 2015 - Comments: 0

A handful of big semiconductor companies began taking the wraps off 2.5D and fan-out packaging plans in the past couple of weeks, setting the stage for the first major shift away from Moore's Law in 50 years. Those moves coincide with reports of commercial [getkc id="82" kc_name="2.5D"] chips from chip assemblers and foundries that are now under development. There have been indications for... » read more

Advanced IC Packaging Biz Heats Up

By Mark LaPedus - 20 Aug, 2015 - Comments: 0

After a number of false starts and lackluster adoption, the advanced IC packaging market is finally heating up. On one front, for example, a new wave of chips based on advanced [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D"] stacked-die is entering the market. And on another front, the momentum is building for new and advanced 2D packages, such as embedded package-on-package (PoP... » read more

2.5D Creeps Into SoC Designs

By Ed Sperling - 13 Aug, 2015 - Comments: 0

A decade ago top chipmakers predicted that the next frontier for SoC architectures would be the z axis, adding a third dimension to improve throughput and performance, reduce congestion around memories, and reduce the amount of energy needed to drive signals. The obvious market for this was applications processors for mobile devices, and the first companies to jump on the stacked die bandwag... » read more

The Memory And Storage Hierarchy

By Loren Shalinsky - 13 Aug, 2015 - Comments: 0

The memory and storage hierarchy is a useful way of thinking about computer systems, and the dizzying array of memory options available to the system designer. Many different parameters characterize the memory solution. Among them are latency (how long the CPU needs to wait before the first data is available) and bandwidth (how fast additional data can be “streamed” after the first data poi... » read more

What Will 7nm And 5nm Look Like?

By Mark LaPedus - 23 Jul, 2015 - Comments: 0

Citing an assortment of undisclosed manufacturing issues, Intel in July pushed out the introduction of its 10nm chip and process technology to the second half of 2017. This is roughly six or more months later than expected. With the delay at 10nm, [getentity id="22846" e_name="Intel"] also pushed out its process cadence from 2 to 2.5 years. Other foundries, meanwhile, are struggling to keep ... » read more

Moore Memory Problems

By Brian Bailey - 09 Jul, 2015 - Comments: 0

The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with these memories and so they are critical to continued scaling. “The SRAM being used in modern systems is similar to the SRAM they were using in the 1970s and 1980s,” says Duncan Bremner, ch... » read more

Rethinking The Cloud

By Ed Sperling - 12 Mar, 2015 - Comments: 0

Data center architectures have seen very few radical changes since the commercial introduction of the [getentity id="22306" comment="IBM"] System/360 mainframe in 1964. There have been incremental improvements in speed and throughput over the years, with a move to a client/server model in the 1990s, but from a high level this is still an environment where data is processed and stored centrally ... » read more

Partition Lines Growing Fuzzy

By Ed Sperling - 26 Feb, 2015 - Comments: 0

For as long as most semiconductor engineers can remember, chips with discrete functions started out on a printed circuit board, progressed into chip sets when it made sense and eventually were integrated onto the same die. The primary motivations behind this trend were performance and cost—shorter distance, fewer mask layers, less silicon. But this equation has been changing over the past ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?