Will Hypervisors Protect Us?

By Brian Bailey - 25 Aug, 2016 - Comments: 2

Another day, another car hacked and another report of a data breach. The lack of security built into electronic systems has made them a playground for the criminal world, and the industry must start becoming more responsive by adding increasingly sophisticated layers of protection. In this, the first of a two-part series, Semiconductor Engineering examines how hypervisors are entering the embed... » read more

Engineering Challenges Of ADAS

By Andrew Macleod - 04 Aug, 2016 - Comments: 0

Advanced driver assistance systems (ADAS) have made tremendous strides in the past decade. The technology is part of the larger thrust to improve safety of cars, which cause over a million deaths per year around the world. Fortunately, fatal crashes have been on a steady decline for decades even as automobile usage has gone up. This is due in large part to safety-related technologies, including... » read more

Securing The Cloud

By Ernest Worthman - 03 Mar, 2016 - Comments: 0

Cloud computing offers on-demand network access that is ubiquitous and convenient, with a pool of configurable computing resources such as shared networks, servers, storage, applications, and services. What makes this so attractive is these services can be provisioned and adapted to the load, with minimal management or service provider intervention. Cloud computing takes advantage of a distr... » read more

More Uses For Hypervisors

By Ann Mutschler - 14 Jan, 2016 - Comments: 0

Hypervisors are showing up in more places than ever before as a quick and inexpensive way to utilize multiple cores and multiple chips more effectively and more securely. This marks an interesting twist for a technology that originally was developed as a way of enabling virtualization on a PC, allowing users to run multiple incompatible applications on the same computer. That was followed in... » read more

The Great IoE Race Begins

By Ed Sperling - 05 Nov, 2015 - Comments: 0

Nobody knows how many tens of billions of semiconductors will be used in the IoE, but it's a sure bet it won't be a few chips replicated billions of times. Most IoE devices will need to be customized for specific applications. Many will need to be highly reliable for many years. And all of them will need to be secure and power-efficient. Yet they also will need to connect to heterogeneous ne... » read more

Challenges For IC Security

By Ernest Worthman - 05 Feb, 2015 - Comments: 0

Keeping chips secure is really a foot race between the good guys and the bad guys. Going forward, expect heavily funded, grouped efforts to place tremendous pressure on security envelopes. This includes everything from simple home devices, such as routers, to the most critical infrastructures, such as power, telecom, transportation, and soon, the IoT. Fig. 1: Courtesy of Blade Genexis I... » read more

Week In Review: System-Level Design

By Ed Sperling - 25 Oct, 2013 - Comments: 0

Mentor Graphics unveiled an embedded hypervisor for automotive infotainment systems. This is a Type 1 hypervisor, meaning it runs next to the metal and below the OS. In contrast, Type 2 hypervisors run above the OS. Mentor’s hypervisor supports multicore processors and ARM’s TrustZone security. Synopsys rolled out Ethernet controller IP for the data center, focused on energy efficiency a... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer