tag: IBM

Hypervisors For Managing Power
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Ed Sperling Hypervisors are headed for a new role inside of multicore chips—managing the various power islands in addition to the cores. A patent application filed by IBM, entitled “Method and syarstem for hypervisor based power management,” shows the company’s intention to use hypervisors for everything from monitoring power consumption rates to scaling power for individual core... » read more

Outsourcing’s New Face
By Ed Sperling - 29 Oct, 2009 - Comments: 0

By Ed Sperling As the semiconductor industry digs out from one of the worst downturns in decades, the business of semiconductor design and engineering is changing. While the architecture and features are still being developed by chip companies, the actual work of developing the chip increasingly is being done by third parties. Outsourcing is hardly new concept in business. In the early pa... » read more

Making Connections
By Ed Sperling - 28 Oct, 2009 - Comments: 0

By Ed Sperling The world is still full of engineers who can build fast interconnects to things like PCI Express or USB 2.0 who can create complex schematics for determining the connections between a processor core, memory, logic and various IP blocks on a piece of silicon. But over the next several years, many of those engineers will have to figure out new ways to make a living. The numbe... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 15 Oct, 2009 - Comments: 0

Low-Power Design sat down with Leon Stok, EDA director for IBM’s System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys’ Implementaton Group; Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta. What follows are excerpts of that conversation. By Ed Sperling LPD: Where... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 02 Oct, 2009 - Comments: 0

Low-Power Design sat down with Leon Stok, EDA director for IBM’s System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys’ Implementaton Group; Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta. What follows are excerpts of that conversation. LPD: What will happen with ... » read more

The Next Big Thing, And Who Will Own It
By Ed Sperling - 24 Sep, 2009 - Comments: 0

At the beginning of this decade a writer for a powerful newspaper told me that, come hell or high water, she wasn’t giving up print—no matter how important online got to be. I had to think about that for awhile before answering, “It may not be your choice.” That newspaper is now a shadow of what it once was, but the statement keeps reminding me of some of the brash claims being mad... » read more

Experts At The Table: Evolving Standards
By Ed Sperling - 24 Sep, 2009 - Comments: 0

System-Level Design sat down with Keith Barkley, senior engineer in IBM’s systems and technology group; Steven Schulz, president and CEO of Silicon Integration Initiative (Si2); Yatin Trivedi, director of standards and interoperability programs at Synopsys; Ian Mackintosh, chairman of the OCP International Partnership (OCP-IP), and Michael Meredith, vice president of technical marketing at ... » read more

End User Report: The Case For Formalizing Power Modeling
By Ed Sperling - 17 Sep, 2009 - Comments: 0

While the industry clearly agrees that power modeling is a necessity for next-generation semiconductor design at the transaction level, what is lacking is a standard way to exchange power models. Low-Power Design talked with David Hathaway, Senior Technical Staff Member at IBM Electronic Design Automation and Nagu Dhanwada, Senior R&D Engineer and Team Lead for Chip Level Power Analysis T... » read more

Moore’s Law vs. Low Power
By Ed Sperling - 17 Sep, 2009 - Comments: 0

By Ed Sperling Moore’s Law and low-power engineering are natural-born enemies, and this dissension is becoming more obvious at each new process node as the two forces are pushed closer together. The basic problem is that shrinking transistors and line widths between wires opens up far more real estate on a chip, which encourages chip architects and marketing chiefs at chipmakers to take... » read more

Experts At The Table: What’s Next?
By Ed Sperling - 17 Sep, 2009 - Comments: 0

Low-Power Design sat down with Leon Stok, EDA director for IBM’s System & Technology Group; Antun Domic, senior vice president and general manager of Synopsys’ Implementaton Group; Prasad Subramaniam, vice president of design technology at eSilicon, and Bernard Murphy, chief technology officer at Atrenta. What follows are excerpts of that conversation. LPD: What are we facing at ... » read more

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