Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards

By Martin James, Gary Dick, and Arif Khan, Cadence with Suhas Pai and Brian Rea, Intel The Compute Express Link™ (CXL™) 2.0 specification, released in 2020, accompanies the latest PCI Express (PCIe) 5.0 specification to provide a path to high-bandwidth, cache-coherent, low-latency transport for many high-bandwidth applications such as artificial intelligence, machine learning, ... » read more

Pushing The Limits Of Hardware-Assisted Verification

As semiconductor complexity continues to escalate, so does the reliance on hardware-assisted simulation, emulation, and prototyping. Since chip design first began, engineers have complained their design goals exceeded the capabilities of the tools. This is especially evident in verification and debug, which continue to dominate the design cycle. Big-iron tooling has enabled design teams to k... » read more

A Complete System-Level Security Verification Methodology

Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

Automakers Take On More Responsibility

Chip and EDA companies are scrambling to deal with stiff safety regulations and harsh environmental conditions for automotive chips, but automakers are making big changes of their own to ensure all those components work together as expected. The result is a significant shift of responsibilities of companies in the automotive supply chain. Carmakers traditionally have left verification, valid... » read more