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A Complete System-Level Security Verification Methodology

A collaboration provides a security verification platform capable of detecting system-level vulnerabilities requiring minimal disruption to existing functional flows.

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Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requires a significant shift in strategy because security vulnerabilities often exploit unintended or unspecified functionality. Because of these challenges, there is currently no systematic, scalable, and effective methodology for pre-silicon security verification. Tortuga Logic and Cadence have collaborated to provide a security verification platform capable of detecting system-level vulnerabilities requiring minimal disruption to existing functional flows.

Cadence/Tortuga Logic white paper: SOC security verification method

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By Dr. Nicole Fern, Senior Hardware Security Engineer, Tortuga Logic; Steve Carlson, Director, Aerospace and Solutions Architect, Cadence.



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